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* chiselTests: include an example of two empty Vectors killing FIRRTL
* Aggregate: fix a bug whereby Vec[T] was using equals/hashCode of Seq
In Chisel, two vectors are NOT equal just if their contents are equal.
For example, two empty vectors should not be considered equal. This
patch makes Vec use the HasId._id for equality like other Chisel types.
Without this fix, Bundle.namedElts.seen: HashSet[Data]() will eliminate
one of the named vectors and emit bad IR.
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Source locators
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This prevents Verilator from erroring when it cannot determine the top-module.
It also changes the PRINTF_COND guard to correctly use the top-level reset
instead of just the top of the Chisel-generated code.
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remove Tester.scala
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chisel-testers repo
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RegNext and RegInit should match Reg(next=) and Reg(init=)
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Option(null) returns None, but Some(null) returns Some(null)
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Move emit out of IR
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The return value of Bits.toBools doesn't need to be dynamically indexed
(as you could have just dynamically indexed the Bits itself), so
returning a Seq instead of a Vec is mroe appropriate.
This breaks a circular dependence between Bits and Vec, which helps
with macros/frontend refactoring.
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Include Chisel Frontend in JAR
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Seq to variatic argument list
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for source locator macros
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Closes #90
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Partially resolves #164
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@aswaterman closes #156
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Setting the io ref there wasn't doing anything meaningful
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The old blackbox behavior still emitted extmodules that have a
clk, reset pin and prepended all io's with io_ (ultimately). Most
verilog modules do not follow this distinction (or use a slightly
different name for clock and so on).
Thus, instead BlackBox has been rewritten to not assume a clk or
reset pin. Instead, the io Bundle specified is flattened directly
into the Module.ports declaration. The tests have been rewritten
to compensate for this. Also, added a test that uses the clock pin.
As a secondary change, the _clock and _reset module parameters were
bad for two reasons. One, they used null as a default, which is a
scala best practices violation. Two, they were just not good names.
Instead the primary constructor has been rewritten to take an
Option[Clock] called override_clock and an Option[Bool] called
override_reset, which default to None. (Note how the getOrElse call
down below is much more natural now.)
However, users may not want to specify the Some(their_clock) so I
also added secondary constructors that take parameters named clock
and reset and wrap them into Some calls into the primary constructor.
This is a better UX because now you can just stipulate clock=blah in
instantiation of that module in symmetry with using the clock in the
definition of the module by invoking clock.
PS: We could also back out of allowing any overrides via the Module
constructor and just require the instantiating Module to do
submodule.clock := newclock, etc.
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Often times the scala runtime reflection fails to find an appropriate
name for a given net. This commit tries to partially ameliorate the
issue by exposing a suggestName function onto HasId (i.e. Module, Data)
that the user can call to 'suggest' a name.
Only the first suggestion is taken so repeated calls to suggestName will
not change the name for that node. This type of name exposure is
slightly risky as there is a chance the same name is suggested in the
same namespace. Thus, naming within a Module occurs in two passes:
The suggestion phase is when the user calls suggestName, etc. Near the
'end,' the Module uses runtime reflection to suggest names as well.
The forcing phase is when all the nodes are run through and a name is
'forced' onto them, using the namespace to suggest alternatives if the
desired one is taken. If no suggestion is present, the default name is
T, as before.
Second, there is an issue that commonly comes up when a component
library creates intermediate logic and then only returns a piece, or
even a piece of a piece (like part of a module IO). Any names suggested
by the Module by reflection onto that return value are either lost or
not fully applied. This issue is resolved by TransitName. TransitName
attaches a hook to the suggestName function of a HasId. With that hook,
any time suggestName is called on the hooked ID, that name suggestion is
also applied to other nodes.
For example, if Queue(in) is called, then any attempts to name the
returned output DecoupledIO will actually translate to naming attempts
on the backing Queue.
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more kind assert on chiselMain
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I had a def instead of a val.
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One could make an argument for disallowing n=0, too, but HW generators
will benefit from our leniency.
Closes #107. Thanks @jackkoenig
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Users should assume it's OK to make them expensive to evaluate.
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It's an unconvincing means to pretend there isn't mutable state when
there really is. It's more confusing and less performant than just
calling a spade a spade.
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Mathematically, we should also reject 0, like log2Ceil does. But accepting
0 and returning 1 is more in the spirit of the special case for widths.
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This makes chisel2's behaviour and makes it
easier to read large constants.
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There's a separate debate to be had about whether we want to
default-initialize Wires to invalid. This patch just fixes the
implementation of the previous, unsafe approach, which was usually,
but not always, defaulting to invalid.
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Bump plugin versions.
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