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AgeCommit message (Expand)Author
2018-09-07Bump scopt from 3.6.0 -> 3.7.0 (#877)Schuyler Eldridge
2018-08-31Support for verilog memory loading. (#840)Chick Markley
2018-08-29Inhibit aggressive resource file name mangling. (#884)Jim Lawson
2018-08-23Merge pull request #838 from seldridge/issue-602Jack Koenig
2018-08-23Add FlattenInstance APISchuyler Eldridge
2018-08-23Add InlineInstance APISchuyler Eldridge
2018-08-22Update class name in error messageEdward Wang
2018-08-22Implement varargs MixedVec APIEdward Wang
2018-08-22Make MixedVec wire init consistent with VecInitEdward Wang
2018-08-22Remove dynamic indexing for nowEdward Wang
2018-08-22Use a mix-in to override Seq errorEdward Wang
2018-08-22MixedVec: clarify dynamic indexing of heterogeneous elementsEdward Wang
2018-08-22Warn user that using Seq for hardware construction in Bundle is not supportedEdward Wang
2018-08-22Remove redundant := methodEdward Wang
2018-08-22MixedVec implementationEdward Wang
2018-08-22Minor tweaks to the style guide (#876)edwardcwang
2018-08-21Bump to Scala 2.12.6 and make it the default. (#858)Jim Lawson
2018-08-07BoringUtils / Synthesizable Cross Module References (#718)Schuyler Eldridge
2018-07-31Cleanup implicit conversions (#868)Jack Koenig
2018-07-31Ensure names work for bundles and literals. (#853)Jim Lawson
2018-07-31Revert removal of bit extraction const prop for literals (#857)Jack Koenig
2018-07-26Update latest release. (#863)Jim Lawson
2018-07-19Add support for Input() and Output() (available in Chisel2 since ucb-bar/chis...Jim Lawson
2018-07-11Update versions and links in README (#855)Jack Koenig
2018-07-10Fix use of read-only refs on rhs of connect in compatibility mode (#854)Jack Koenig
2018-07-09Bump recommended Verilator version to 3.922 (#851)Jim Lawson
2018-07-06Undeprecate log2Up and log2Down (#846)Jack Koenig
2018-07-05Ignore eclipse temporariesRichard Lin
2018-07-04Change wording of internal failureRichard Lin
2018-07-04Fix strict namerRichard Lin
2018-07-04Remove forceName rom BlackBox/ExtModule, filter out forceName in UserModuleRichard Lin
2018-07-04Add test that UInt, SInt, and FP literals do not impact namingJack Koenig
2018-07-04Prefer litValue, eliminate litToBigIntducky
2018-07-04Change [public] Data.elementLitArg => [protected] Aggregate.litArgOfBitsducky
2018-07-04Style fixesducky
2018-07-04binding => topBinding so that partial Bundles work and undefined Bundle membe...ducky
2018-07-04properly fix undefined clock/reset issuesducky
2018-07-04Add BundleLiteralSpecRichard Lin
2018-07-04Comment out assertion test, fix ref generationRichard Lin
2018-07-04Add new test LitInsideOutsideTesterchick
2018-07-04unbrokenducky
2018-07-04still brokenducky
2018-07-04brokenducky
2018-07-04delete debugging stuffducky
2018-07-04styleducky
2018-07-04Run-unique idsducky
2018-07-04lol=(Richard Lin
2018-07-04bundle literal mockup, but broken =(Richard Lin
2018-07-04refactoring of lit and ref implementationsRichard Lin
2018-07-04work on new style literal accessorsducky
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