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AgeCommit message (Expand)Author
2022-03-08Add scanLeftOr and scanRightOr utilies (#2407) (#2437)mergify[bot]
2022-03-07Tweaks to the Verilog-vs-Chisel Page (#2432) (#2433)mergify[bot]
2022-03-04Add SVG Version of Bundle Example Diagram (#2425) (#2431)mergify[bot]
2022-03-04Issue errors on out-of-range extracts when width is known (#2428) (#2429)mergify[bot]
2022-03-03Add Verilog-chisel side by side Reference Page to Docs (#2323) (#2426)mergify[bot]
2022-02-15Make TruthTable accept unknown input width (#2387) (#2417)mergify[bot]
2022-02-11Hierarchy API: make Mems lookupable (#2404) (#2410)mergify[bot]
2022-02-10Make Tuple2 Lookupable (#2372) (#2406)mergify[bot]
2022-02-08Overload getVerilogString to accept arguments (#2401) (#2402)mergify[bot]
2022-02-04Fix variable-name typo (#2397) (#2400)mergify[bot]
2022-02-04Fix bundle elements performance regression (#2396) (#2398)mergify[bot]
2022-02-03FillInterleaved documentation: swap order of elements in Seq example (#2393) ...mergify[bot]
2022-02-03Tweak Bundle._elementsImpl (#2390) (#2392)mergify[bot]
2022-02-03Tweak new mem port clock warnings (#2389) (#2391)mergify[bot]
2022-02-02Add Scala 2.13.8 to plugin cross-compilation (#2385) (#2386)mergify[bot]
2022-02-01Improve error reporting (backport #2376) (#2379)mergify[bot]
2022-02-01Optional clock param for memory ports (#2333) (#2382)mergify[bot]
2022-02-01Chisel plugin bundle elements handler (#2306) (#2380)mergify[bot]
2022-01-28Fix Decoder bug for constant 0 and DC (#2363) (#2371)mergify[bot]
2022-01-26Expand supported val modifiers for @public (#2365) (#2367)mergify[bot]
2022-01-20Fix Compatibility Module io wrapping (#2355) (#2358)mergify[bot]
2022-01-20Fix link to Naming Cookbook (#2356) (#2357)mergify[bot]
2022-01-19util: add GrayCode (#2353) (#2354)mergify[bot]
2022-01-17Add 3.5.x to Github Actions push triggersJack Koenig
2022-01-12Update README and PR template for 3.5.0 release (#2339) (#2342)mergify[bot]
2022-01-11Set mimaPreviousArtifacts for binary compatibility checkingJack Koenig
2022-01-11Lookupable: add Either version (#2335)Megan Wachs
2022-01-10Merge pull request #2246 from chipsalliance/scalafmtJack Koenig
2022-01-10Enable scalafmt in CIJack Koenig
2022-01-10Apply scalafmtJack Koenig
2022-01-10Add scalafmt config, SBT plugin, and mill supportJiuyang Liu
2022-01-10Merge pull request #2334 from chipsalliance/update-mergify-queue-actionJack Koenig
2022-01-10Update Mergify config for new queue actionJack Koenig
2022-01-10Add config for generating .mergify.ymlJack Koenig
2022-01-07Add a Select.ios that works with Definition/Instance, fix isA behavior (#2315)Megan Wachs
2021-12-21Update README for 3.5.0-RC2 (#2317)Jack Koenig
2021-12-20Merge pull request #2314 from chipsalliance/fix-unidocJack Koenig
2021-12-20Turn on unidoc checking in CIJack Koenig
2021-12-20[plugin] add -P:chiselplugin:INTERNALskipFileJack Koenig
2021-12-20[plugin] Internal refactor, remove useBundlePluginJack Koenig
2021-12-20Better documentation for := and <> (#2312)Olushola Ogunkelu
2021-12-18Revert "Make stuff in IR.scala package private (#2274)" (#2308)Jack Koenig
2021-12-17Improve exception message for aliased bundle fields (#2304)Chick Markley
2021-12-16BitSet API (#2211)Jiuyang Liu
2021-12-15Restore Port to public API and deprecate (#2302)Jack Koenig
2021-12-15Add "Upgrading From Chisel 3.4 to 3.5" (#2275)Jack Koenig
2021-12-15Update sbt to 1.5.7 (#2303)Scala Steward
2021-12-15Refactor TruthTable to use Seq (#2217)Jiuyang Liu
2021-12-15deprecate getModulePorts (#2284)Jiuyang Liu
2021-12-14Make stuff in IR.scala package private (#2274)Aditya Naik
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