summaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2018-09-28Add dumpAnnotations method to DriverSchuyler Eldridge
2018-09-21Add CODEOWNERS file (#895)Albert Magyar
2018-09-20Documentation tweaksedwardcwang
2018-09-14Give type annotation to litOption. (#887)grebe
2018-09-13Bump version reference in README.md (#888)Jim Lawson
2018-09-07Merge pull request #873 from seldridge/issue-872Schuyler Eldridge
2018-09-07Add ToBoolable ScalaDoc documentationSchuyler Eldridge
2018-09-07Add Element ScalaDoc documentationSchuyler Eldridge
2018-09-07Add FixedPoint ScalaDoc documentationSchuyler Eldridge
2018-09-07Add Bool ScalaDoc documentationSchuyler Eldridge
2018-09-07Add SInt ScalaDoc documentationSchuyler Eldridge
2018-09-07Add UInt ScalaDoc documentationSchuyler Eldridge
2018-09-07Add Num ScalaDoc documentationSchuyler Eldridge
2018-09-07Add Bits ScalaDoc documentationSchuyler Eldridge
2018-09-07Put := and <> methods in Connect ScalaDoc groupSchuyler Eldridge
2018-09-07Put do_* methods in SourceInfoTransformMacro groupSchuyler Eldridge
2018-09-07Enable ScalaDoc groups, ignore chisel3.internalSchuyler Eldridge
2018-09-07Add Logical ScalaDoc group to NumSchuyler Eldridge
2018-09-07Add Comparison ScalaDoc group to NumSchuyler Eldridge
2018-09-07Add Arithmetic ScalaDoc group to NumSchuyler Eldridge
2018-09-07Add Bitwise ScalaDoc group to BitsSchuyler Eldridge
2018-09-07Add Connect ScalaDoc group to DataSchuyler Eldridge
2018-09-07Add SourceInfoDoc trait w/ ScalaDoc groupSchuyler Eldridge
2018-09-07Bump scopt from 3.6.0 -> 3.7.0 (#877)Schuyler Eldridge
2018-08-31Support for verilog memory loading. (#840)Chick Markley
2018-08-29Inhibit aggressive resource file name mangling. (#884)Jim Lawson
2018-08-23Merge pull request #838 from seldridge/issue-602Jack Koenig
2018-08-23Add FlattenInstance APISchuyler Eldridge
2018-08-23Add InlineInstance APISchuyler Eldridge
2018-08-22Update class name in error messageEdward Wang
2018-08-22Implement varargs MixedVec APIEdward Wang
2018-08-22Make MixedVec wire init consistent with VecInitEdward Wang
2018-08-22Remove dynamic indexing for nowEdward Wang
2018-08-22Use a mix-in to override Seq errorEdward Wang
2018-08-22MixedVec: clarify dynamic indexing of heterogeneous elementsEdward Wang
2018-08-22Warn user that using Seq for hardware construction in Bundle is not supportedEdward Wang
2018-08-22Remove redundant := methodEdward Wang
2018-08-22MixedVec implementationEdward Wang
2018-08-22Minor tweaks to the style guide (#876)edwardcwang
2018-08-21Bump to Scala 2.12.6 and make it the default. (#858)Jim Lawson
2018-08-07BoringUtils / Synthesizable Cross Module References (#718)Schuyler Eldridge
2018-07-31Cleanup implicit conversions (#868)Jack Koenig
2018-07-31Ensure names work for bundles and literals. (#853)Jim Lawson
2018-07-31Revert removal of bit extraction const prop for literals (#857)Jack Koenig
2018-07-26Update latest release. (#863)Jim Lawson
2018-07-19Add support for Input() and Output() (available in Chisel2 since ucb-bar/chis...Jim Lawson
2018-07-11Update versions and links in README (#855)Jack Koenig
2018-07-10Fix use of read-only refs on rhs of connect in compatibility mode (#854)Jack Koenig
2018-07-09Bump recommended Verilator version to 3.922 (#851)Jim Lawson
2018-07-06Undeprecate log2Up and log2Down (#846)Jack Koenig
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-01 18:37:31 +0000