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2020-01-23Minor changes - update comments, use MaxBitsBigIntToBigDecimal instead of ↵Jim Lawson
'108'. (#1309) Co-authored-by: Chick Markley <chick@qrhino.com>
2020-01-22Update comment for Clock.asBool()Jim Lawson
2020-01-22Merge branch 'master' into add-asbool-to-clockChick Markley
2020-01-22Merge branch 'master' into big-decimal-methods-for-num-typesChick Markley
2020-01-22Change when/switch thunk type to Any (#1308)Schuyler Eldridge
* Change when thunks return type to Any Changes the type of the thunk for when and WhenContext methods from call-by-name Unit to call-by-name Any. This prevents a warning (-Ywarn-value-discard) where a when thunk is returning something other than Unit that is then discarded, e.g., another WhenContext. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Change switch thunk return to type to Any Changes the type of switch thunks from call-by-name Unit to call-by-name Any. This prevents a warning (-Ywarn-value-discard) when the internals of a switch block return something other than Unit which is then discarded. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-01-21Merge branch 'master' into big-decimal-methods-for-num-typeschick
# Conflicts: # src/test/scala/chiselTests/IntervalSpec.scala
2020-01-21Merge branch 'master' into add-asbool-to-clockJim Lawson
2020-01-21Merge pull request #1283 from freechipsproject/fix-bitpat-whitespaceChick Markley
BitPat supports whitespace and underscores
2020-01-21Removed unnecessary castChick Markley
Non-functional, must have been a typo
2020-01-21Merge branch 'master' into add-asbool-to-clockJim Lawson
2020-01-21Merge branch 'master' into fix-bitpat-whitespaceJim Lawson
2020-01-21specifying type of target field (#1305)Deborah Soung
2020-01-17Bugfix: Select.instances now works with blackboxes (#1303)Adam Izraelevitz
2020-01-07Merge branch 'master' into add-asbool-to-clockJim Lawson
2020-01-07Merge branch 'master' into fix-bitpat-whitespaceJim Lawson
2020-01-07Remove over design (#1237)Leway Colin
Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Co-authored-by: Chick Markley <chick@qrhino.com>
2020-01-02Merge pull request #1275 from freechipsproject/interval-fix-2Chick Markley
Fixed problem creating Interval literals with full ranges
2019-12-19Removed accidentally introduced parenschick
2019-12-18Add method asBool to Clock.chick
Shortcut for .asUInt.asBool Added test to show it works
2019-12-18- New trait HasBinaryPoint which provides literal values as double and big ↵chick
decimal - made .F and .I work for creating fixed point and interval lits from big decimal - Added NumObject trait which provides new math conversions - Made a Num object that extends NumObject - Add this trait to FixedPoint and Interval for backward compatibility - Removed code that is now in NumObject, keeping things DRY - Add tests to FixedPointSpec to show lit conversion to double and big decimal - Add tests to IntervalSpec to show lit conversion to double and big decimal - Add tests to LiteralExtractorSpec to show general math conversions between BigInts with binary points and double and big decimal
2019-12-18BitPat supports whitespace and underscores, presumably for human readability.chick
The BitPat.parse factory though did not remove these from the returned count. This fixes that adds whitespace and underscores to the unit tests This is an updated vesion of Chisel PR #1069
2019-12-17Merge branch 'master' into interval-fix-2Chick Markley
2019-12-17Band aid until litOption is implemented for Aggregates. (#1277)Jim Lawson
This is just a band aid until an Aggregate `isLit()` method (for which work has begun) is implemented.
2019-12-16Remove unused WriteEmitted phase (#1273)Schuyler Eldridge
This removes a dead line where a WriteEmitted phase is constructed. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-12-12Fixed problem creating Interval literals with full rangeschick
- boundary testing was not taking binary point into account correctly - add tests to show where things work and where they are supposed to fail
2019-12-11Merge pull request #1274 from freechipsproject/interval-fix-1Chick Markley
Bug fixes to support code for Interval
2019-12-11- add simple test of IntervalRange helperschick
- getLowestPossibleValue - getHighestPossibleValue - getPossibleValues
2019-12-11- Change getPossibleValues of Interval to return a NumericRange former Seq ↵chick
materialized all values - Fixed computation in getHighestPossibleValue, erroneously was using lower intead of upper
2019-12-06Revert "Compat compile options macro (#1253)" (#1268)Jack Koenig
This reverts commit 85fe90d5b7ed4e1101b0b3959a1d362eb93915ac.
2019-12-04Add ChiselEnum to BundleLiterals (#1215)Zhuanhao Wu
2019-12-02Remove Jenkins CI from .mergify.yml (#1264)Jack Koenig
2019-12-02Fix asTypeOf for Clock (#1258)Jack Koenig
2019-11-29Merge pull request #1260 from freechipsproject/ccc20-extensionSchuyler Eldridge
Update README to reflect CCC20 Extension
2019-11-29Update README to reflect CCC20 ExtensionSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-11-29Fix deprecation warning that leaks into user code (#1256)Jack Koenig
Data.isLit called Data.litArg which would trigger a Chisel runtime deprecation warning in user code with source locator Data.scala:488
2019-11-29Compat compile options macro (#1253)Jack Koenig
* Use macro to materialize CompileOptions in Chisel._ This switches from using an implicit val that required awkward suppression (as illustrated in CompileOptionsSpec) to allowing overriding in the same way as done in "import chisel3._" via the creation of an implicit val in lexical scope. * Deprecate Chisel.defaultCompileOptions
2019-11-27Fix bidirectional Wire with Analog (#1252)Jack Koenig
2019-11-22Add binary comp. check to mergify bpAdam Izraelevitz
2019-11-22Fix mergify to backports: omit jenkins CI (#1246)Adam Izraelevitz
2019-11-22Create .mergify.yml (#1244)Adam Izraelevitz
2019-11-21Add CCC20 Info at README top (#1243)Schuyler Eldridge
* Add CCC20 Info at README top Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add Upcoming Events h2 Heading to README.md Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-11-17Improve error message when assigning from Seq to Vec (#1239)Andrew Waterman
2019-11-15Enable @chiselName on non-module classes (#1209)John's Brew
2019-11-12Add brief description of (current) chisel versioning and version ↵Jim Lawson
recommendations. (#1180) * Add brief description of (current) chisel versioning and version recommendations. * Respond to comments. Replace "semantic versioning" with "a form of semantic versioning". * Respond to comments - replace mmddyy with yyyymmdd. * Mention change in SNAPSHOT naming.
2019-11-06Merge pull request #1201 from freechipsproject/full-MuxLookupSchuyler Eldridge
Don't use MuxLookup default for full mapping
2019-11-05Add tests for exhaustive MuxLookup optimizationAlbert Magyar
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2019-11-05Don't use MuxLookup default for full mappingSchuyler Eldridge
This modifies MuxLookup to not use the 'default' mapping argument if a "full" mapping is provided. A "full" mapping enumerates all possible cases for a 'key' argument of a known size. This will check literal values to ensure exhaustiveness holds. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2019-11-05Support literals cast to aggregates as async reset reg init values (#1225)Jack Koenig
Accomplished by changing the code gen for casting literals to aggregates. Rather than connecting the literal to a wire that is then bit selected from, just bit select from the literal which saves the creation of an intermediate wire and matches FIRRTL's semantics for legal async reset initial values.
2019-11-05Bump master SNAPSHOT version. (#1227)Jim Lawson
2019-11-02Merge pull request #1224 from freechipsproject/issue-1223Schuyler Eldridge
Improve naming of anonymous/class-in-function Modules
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