summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2020-03-26Set StageError cause in ChiselStage (#1382)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
2020-03-25Merge pull request #1384 from freechipsproject/no-more-compile-internalJack Koenig
No more compile internal
2020-03-25Rename subprojects to more canonical namesJack Koenig
* Rename coreMacros to macros * Rename chiselFrontend to core Also make each subproject publish with "chisel3-" as a prefix
2020-03-25Remove compile-internal from build.sbtJack Koenig
This has the effect of causing the coreMacros and chiselFrontend projects to be published separately
2020-03-24Propagate user compile options for Chisel.Module (#1387)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-03-24Merge pull request #1213 from freechipsproject/driver-deprecationsSchuyler Eldridge
Deprecate Driver methods in favor of ChiselStage
2020-03-24Update README.md to reference ChiselStageSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-24Add ChiselStageSpec for string/circuit emissionSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-24Add helper methods to ChiselStage for Driver migrationSchuyler Eldridge
This adds three new methods to ChiselStage to replace deprecated methods in the Driver for converting a Chisel circuit to a string: - emitChirrtl - emitFirrtl - emitVerilog This also adds a ChiselStage companion object that lets you generated a Chisel Circuit or a FIRRTL Circuit from a Chisel module: - elaborate - convert Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> squash! Add string emission helper methods to ChiselStage
2020-03-24Deprecate Driver methods in favor of ChiselStageSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-23Remove toNamed (and friends) deprecation. (#1377)Jim Lawson
* Remove toNamed (and friends) deprecation. * Add inadvertently deleted leading double quote. * Remove commented out deprecations.
2020-03-23Add NoChiselNamePrefix to ignore instances in @chiselName (#1383)Jack Koenig
Add trait chisel3.experimental.NoChiselNamePrefix which causes @chiselName to skip naming of the instance effectively preventing it from prefixing any vals inside the instance. It can be applied to classes such that all instances of that class have this property, or to individual instances (via creating an anonymous class inline). Also add basic ScalaDoc for NoChiselNamePrefix and chiselName.
2020-03-21Use innermost builder cause to trim stack trace (#1380)Schuyler Eldridge
Change the logic for determining which nested ChiselException cause to use for a trimmed stack trace. Previously, this would use the outermost. This commit changes this to use the innermost. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-19Merge pull request #1374 from freechipsproject/dont-wrap-elaboration-annotationsSchuyler Eldridge
Don't wrap elaboration annotations
2020-03-19Add Scaladoc to ChiselExceptionSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-19Safer generation of ChiselException.builderNameSchuyler Eldridge
Change ChiselException.builderName to compute the name of Chisel's internal Builder as opposed to hard-coding this with a string. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-19Code style improvementSchuyler Eldridge
Co-authored-by: Jack Koenig <koenig@sifive.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-19Test nested ChiselException in ChiselMainSchuyler Eldridge
Adds two tests: 1. Test that an internal requirement failure (a bare exception) inside a Builder is properly reported/trimmed by ChsielStage/ChiselMain 2. Test that the full stack trace includes the ChiselException Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-19Report trimmed stack trace of Builder causeSchuyler Eldridge
Changes the behavior of ChiselException stack trace trimming to use either the first exception that includes a method from the Builder or the outer exception. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-11Wrap elaboration in ChiselExceptionSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> squash! Wrap elaboration in ChiselException
2020-03-10[mergify] Update match string for labeling backported PRs (#1373)Albert Magyar
2020-03-08Merge pull request #1372 from freechipsproject/mergify-ignore-bp-conflictsAlbert Magyar
Make mergify open backport PRs & signal on failed cherry-picks
2020-03-08Label & block conflicting backport PRsAlbert Magyar
2020-03-06Make mergify open backport PRs & signal on failed cherry-picksAlbert Magyar
2020-03-06Make implicit clock and reset final vals (#1360)Jack Koenig
Overriding will always result in a NullPointerException
2020-03-06Provide API to set concrete type of implicit reset (#1361)Jack Koenig
Introduces mutually-exclusive traits RequireAsyncReset and RequireSyncReset to set the type of the implicit reset in MultiIOModules. The Scala-type remains Reset, but the Chisel elaboration-time checks apply. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-03-02Cleanup aspects (#1359)Adam Izraelevitz
* Clean up aspects * Refactored InjectingAspect with InjectorAspect * Made AspectLibrary work with objects * Cleaned up code * Apply suggestions from code review * Added tests, removed deprecated newInstance call * Backed out removal of newInstance as exceptions were different * Removed trailing commas
2020-02-28Retain default version assignment (#1365)Jim Lawson
The release process uses python to scan and set expected versions for a release. The `val defaultVersions = ` stanza should be present for this to work.
2020-02-21mill: add testOnly (#1357)Sequencer
2020-02-21mill: sbt-compatible publishing (#1356)Sequencer
2020-02-19Merge pull request #1270 from freechipsproject/dependency-api-2Schuyler Eldridge
Migrate to Dependency Wrapper
2020-02-19Migrate to Dependency WrapperSchuyler Eldridge
This changes Phase dependency specification to use the new Dependency wrapper. Previously, dependencies were specified as classes. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-19Patch fix #1109 (#1346)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-19Upcoming Events: Remove CCC, add Dev Meetings (#1345)Schuyler Eldridge
* Remove CCC Upcoming Event Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add developer meetings as upcoming events Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-13Fix mill build (#1324)Sequencer
* add mill build * add gitignore and mill version
2020-02-12Fix := of Reset and AsyncReset to DontCare (#1336)Jack Koenig
2020-02-11Clone child elements lazily in Vec (#1329)Jack Koenig
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2020-02-11Bump sbt and tool/plugin dependencies. (#1332)Jim Lawson
2020-02-10Make Queue.irrevocable work properly in chisel3Edward Wang
Close #1134
2020-02-10Printf: Add support for tabs, and give helpful error messages (#1323) (#1326)Jack Koenig
Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-08README: have a link to the classic tutorial (#1325)Martin Schoeberl
2020-02-06Merge pull request #1315 from freechipsproject/emit-orr-andrSchuyler Eldridge
Emit FIRRTL andr, orr for Bits.{andR, orR}
2020-02-06Emit FIRRTL andr, orr for Bits.{andR, orR}Schuyler Eldridge
Change the emission strategy for Bits methods andR and orR to emit FIRRTL bitwise reduce operations andr and orr. Add two tests that assert the correct behavior of these operations in BitwiseOpsSpec. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-05Add information about widths to RegNext (#1318)Schuyler Eldridge
Adds additional Scaldoc to the RegNext object that (1) indicates that the width is not set and (2) shows an example of how to construct a RegNext-like construct with a set width. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-03Add read-under-write parameter to SyncReadMem (#1183)Albert Magyar
* Add support for readUnderWrite to SyncReadMem * Add write collision behavior test to MemorySpec * Update constant names
2020-02-03Merge pull request #1285 from freechipsproject/add-asbool-to-clockChick Markley
Add method asBool to Clock.
2020-01-31Merge branch 'master' into add-asbool-to-clockChick Markley
2020-01-25Fixed code example typo in comment (#1294)Leway Colin
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-01-25Remove redundancy code (#1296)Leway Colin
* Remove redundancy code * Remove blank line * BitPat supports whitespace and underscores, presumably for human readability. The BitPat.parse factory though did not remove these from the returned count. This fixes that adds whitespace and underscores to the unit tests This is an updated vesion of Chisel PR #1069 Co-authored-by: Chick Markley <chick@qrhino.com> Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-01-23Merge pull request #1284 from freechipsproject/big-decimal-methods-for-num-typesChick Markley
Provides Double and BigDecimal methods to access literal values for FixedPoint and Interval
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-01 20:22:40 +0000