chiselX - Chisel with SFC compatibility

Age	Commit message (Collapse)	Author
2015-10-01	Merge pull request #11 from ucb-bar/removemu	Adam Izraelevitz
	Remove unused emulator C++ headers
2015-09-30	Add documentation to publish local, expand document skeleton	ducky

2015-09-28	Remove cross compilation targets (Chisel3 is Scala 2.11 or later).	Jim Lawson

2015-09-25	Improve coverage of default cloneType method; add comments	Andrew Waterman

2015-09-24	Add new-style Vec constructor; deprecate old version	ducky

2015-09-23	Eliminate outdated parts of readme, add skeleton for new format	ducky

2015-09-23	Remove unused files	ducky

2015-09-22	Integrate Chisel2 Queue scaladoc and formatting changes.	Jim Lawson

2015-09-18	Improve IR class hierarchy	Andrew Waterman
	- Rename Alias to Node to match FIRRTL notion - Remove poorly-named Immediate and replace root of hierarchy with Arg
2015-09-18	Correct some scaladoc comments	Andrew Waterman

2015-09-18	Use FIRRTL idiom for SeqMem read-enables	Andrew Waterman
	Emit read-enables as mux(ren, addr, poison).
2015-09-01	Add scaladoc to UInt/SInt companion objects	Andrew Waterman

2015-09-01	Disallow external use of Vec/UInt/SInt constructors	Andrew Waterman
	Use the companion objects instead.
2015-08-31	Fix val io = new Bundle{...}.flip	Andrew Waterman
	Now, we emit all I/Os inside a bundle named io.
2015-08-31	FIRRTL keywords don't need to be name-mangled, AFAICT	Andrew Waterman

2015-08-31	Fix Namespace bug	Andrew Waterman
	A mangled name may itself conflict with another name.
2015-08-31	Refactor Namespace	Andrew Waterman
	No need for Option, since an empty Set can be used instead.
2015-08-28	Remove references to currently non-working test repos.	Jim Lawson

2015-08-28	Use FIRRTL smem for SeqMem	Andrew Waterman
	Read enables and read-write ports aren't working yet.
2015-08-28	Add poison node	Andrew Waterman

2015-08-27	Redefine masked Mem writes for Mem[Vec]	Andrew Waterman

2015-08-27	Fix bug where flipping top-level I/O had no effect	Andrew Waterman
	The fix is to propagate the flip to the fields in the bundle.
2015-08-27	Vec.apply is for types; Vec.fill is for rvalues	Andrew Waterman

2015-08-27	Expose ChiselExceptions	Andrew Waterman

2015-08-27	Removed reference to filter.	Jim Lawson

2015-08-27	Merge pull request #10 from ucb-bar/scaladoc	Jim Lawson
	Scaladoc - 'when' and Utils
2015-08-27	Add chisel2 scaladoc for 'when'.	Jim Lawson

2015-08-27	Add chisel2 scaladoc for 'library' code.	Jim Lawson

2015-08-26	Remove Mem from Data hierarchy	Andrew Waterman
	Just like Reg, state elements are not Data.
2015-08-26	Simplify Module internal data structures	Andrew Waterman

2015-08-26	Simplify I/O zero-initialization	Andrew Waterman

2015-08-26	Merge pull request #9 from ucb-bar/scaladoc	Jim Lawson
	import relevant scaladoc from chisel(2).
2015-08-26	import relevant scaladoc from chisel(2).	Jim Lawson

2015-08-20	Clean up port emission	Andrew Waterman

2015-08-20	Prevent some defs from being marked as Bundle fields	Andrew Waterman

2015-08-20	Remove Port/Kind IR nodes, which merely wrap Data	Andrew Waterman

2015-08-17	Delete unused IR nodes	Andrew Waterman

2015-08-14	more tests	Henry Cook

2015-08-14	VecShiftReg test	Henry Cook

2015-08-14	todo	Henry Cook

2015-08-14	Add Vec tests. Do a better job of generating widths.	Henry Cook

2015-08-14	added MulLookup and Tbl tests	Henry Cook

2015-08-13	add decoder test	Henry Cook

2015-08-13	Counter tests	Henry Cook

2015-08-13	Make error reporting reentrant	Andrew Waterman

2015-08-13	Deduplicate modules	Andrew Waterman
	This reduces FIRRTL output substantially for e.g. multicore designs.
2015-08-13	Make temporary names locally unique, rather than globally so	Andrew Waterman

2015-08-13	complexassign test	Henry Cook

2015-08-13	Add back missing () on toBits declaration	Andrew Waterman

2015-08-13	Tighten permissions on some classes & members	Andrew Waterman