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2019-08-19Refactor: remove redundant code (#1152)Leway Colin
* Refactor: remove redundant code * Change to protected API * Remove type hierarchy
2019-08-15Merge pull request #1155 from freechipsproject/dependency-apiSchuyler Eldridge
Dependency API (take 2)
2019-08-13Use a PhaseManager for Driver internalsSchuyler Eldridge
Migrate Driver to use a PhaseManager to internally resolve Phase ordering. This requires the use of an identity node to adequately describe the necessary prerequisite/dependents. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2019-08-13Migrate ChiselStage to use the DependencyAPISchuyler Eldridge
Modifies ChiselStage to use a PhaseManager for Phase ordering. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2019-08-13Add Dependencies for Chisel PhasesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2019-08-13Add support for asynchronous reset (#1011)Jack Koenig
Adds new AsyncReset and "abstract" Reset types. Reset is inferred in FIRRTL to be either AsyncReset or Bool. The "reset type" of a register is set by the type of its reset signal: val asyncReset: AsyncReset = IO(Input(AsyncReset())) val syncReset: Bool = IO(Input(Bool())) val abstractReset: Reset = IO(Input(Reset())) val asyncReg = withReset(asyncReset) { RegInit(0.U) } val syncReg = withReset(syncReset) { RegInit(0.U) } val inferredReg = withReset(abstractReset) { RegInit(0.U) } AsyncReset can be cast to and from Bool. Whereas synchronous reset is equivalent to a mux in front of a flip-flop and thus can be driven by logic, asynchronous reset requires that the reset value is a constant. This is checked in FIRRTL. Inference of the concrete type of a Reset occurs based on the type the Reset's drivers. This inference is very simple, it is simple forward propagation of the type, but it allows for writing blocks and modules that are agnostic to the reset type. In particular, the implicit `reset` value in MultiIOModule and thus Module is now concretely an instance of Reset and thus will be inferred in FIRRTL.
2019-08-12Aspect-Oriented Programming for Chisel (#1077)Adam Izraelevitz
Added Aspects to Chisel, enabling a mechanism for dependency injection to hardware modules.
2019-08-12Merge pull request #1151 from colin4124/patch1Schuyler Eldridge
Remove "-Xcheckinit" from build.sc
2019-08-12Use java.lang.NullPointerException other than scala.UnitializedFieldErrorcolin4124
2019-08-08Merge pull request #1148 from freechipsproject/vec-vec-chisel-type-messageSchuyler Eldridge
Require target is hardware for Vec.apply(a: UInt)
2019-08-08Require target is hardware for Vec.apply(a: UInt)Schuyler Eldridge
Adds a check that a Vec being indexed by a UInt is, in fact, a hardware type. This includes a test for this. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-08Merge pull request #1149 from freechipsproject/azidar-patch-1Schuyler Eldridge
Update website references to the new website
2019-08-08Update website references to the new websiteAdam Izraelevitz
2019-08-06Merge pull request #1147 from freechipsproject/lfsr-async-resetSchuyler Eldridge
Avoid when(reset) construct in LFSR
2019-08-06Avoid when(reset) construct in LFSRAndrew Waterman
Muxes and resets are only isomorphic with synchronous reset. Use a reset instead of a conditional to make this async-reset-safe.
2019-08-01Merge pull request #1139 from freechipsproject/deprecations-are-serious-businessSchuyler Eldridge
Remove Deprecations since before 3.2
2019-08-01Flatten *FactoryBase hierarchySchuyler Eldridge
This renames all *FactoryBase traits to *Factory, removes transparent *Factory objects, and propagates this flattened hierarchy throughout the codebase. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-01Remove anything deprecated since before 3.2Schuyler Eldridge
Anything removed by this that is used by the compatibility layer is migrated to the compatibility layer. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Fix deprecated Vec usage in chisel3.util.LFSR16Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Clarify Module deprecationsSchuyler Eldridge
This adds a clarification to the deprecation message for RawModule, MultiIOModule, UserModule, and ImplicitModule. While these were technically deprecated "since the beginning of time", this adds a comment that these aliases will be removed in 3.3. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Fix deprecation warningsSchuyler Eldridge
Change "since" specification from "chisel3.2" to "3.2". This aligns with usages in the rest of the codebase. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Merge pull request #1143 from ↵Schuyler Eldridge
freechipsproject/improve-compatibility-mode-testing Improve compatibility mode testing
2019-07-31Add SInt deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add UInt deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Bits deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add VecLike deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Wire deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Data deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add debug deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Mem/SeqMem deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add LFSR16 deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Queue deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Enum deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add BitPat deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Merge pull request #1142 from freechipsproject/enable-dummy-compatibility-testSchuyler Eldridge
Fixup and enable Dummy CompatibilitySpec test
2019-07-31Fixup and enable Dummy CompatibilitySpec testSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-01Fix shift register in READMEAdam Izraelevitz
2019-07-30Merge pull request #1138 from freechipsproject/core-deprecate-3.2Schuyler Eldridge
Core deprecation "since" should be "3.2" not "3.3"
2019-07-30Change core deprecation "since" from 3.3 -> 3.2Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-24Merge pull request #1129 from freechipsproject/num-maxwidthSchuyler Eldridge
Fix Num.+ Scaladoc
2019-07-24Fix Num.+ ScaladocSchuyler Eldridge
Change Num.+ Scaladoc to state that this is not a growing addition. Note that this is problematic either way as this macro is resolved to an abstract method. Classes implementing this typeclass are technically free to violate what we put in the Scaladoc here. h/t @kammoh Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-18Support Analog DontCare bulk-connect (#1056)Richard Lin
Short-term patch to enable this useful behavior. In the future, we may want to rearchitect the type system and/or rethink the more edge-case connect behavior.
2019-07-18Add width utility functions to avoid incorrect usage of bare log2Ceil(). (#819)Jim Lawson
* Add width utility functions to avoid incorrect usage of bare log2Ceil(). * Respond to comments: Remove apply(Data) method. Change name(s) to signedBitLength, unsignedBitLength. * Respond to comments - don't be lazy. Independently calculate the bit length to verify correct operation. * Respond to comments - return in.bitLength - 0 (not 1) for 0 * Respond to comments - update wdith for signed 0; add explicit tests. * Add comment expressing zero width wire assumption.
2019-07-16Fix typo in README.md (#1123)Henry Cook
2019-06-26Use Verilator 4.016 (#1116)Jim Lawson
* Use Verilator 4.016 Now that ucbbar/chisel3-tools has Verilator 4.016, use that for tests. * Update Verilator version in SETUP
2019-06-24Changed Value macro in ChiselEnum so that it doesn't use deprecated (#1104)Hasan Genc
function. This also fixes prior issue where ChiselEnums would not compile when @chiselName was applied to a module containing a ChiselEnum
2019-06-19First crack at updating the readme (#1106)Chick Markley
* First crack at updating the readme Goals Include up front example Simplify Get users to things quicker Move complicated details to wiki. * headers were not working, intellij and github don't use same render for .md files * Fix verb agreement * Add a fir filter diagram Compact the fir-filter code a bit * More compact filter * Additional README.md updates Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Don't use chisel-lang.org, drop HCL Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Fix link to fir image, make it relative * Proposed readme changes * Resize picture, restyle doc bullets
2019-06-11Added documentation to Decoupled, Conditionals, Counter (#1015)Adam Izraelevitz
* Added documentation to Decoupled, Conditionals, Counter * Fixed private Counter class error * Move Counter class deprecation and re-definition into util package object. * Revert "Move Counter class deprecation and re-definition into util package object." This reverts commit f61bdddf7051522363e1d203fcd46b512047c87d. * Restore the old Counter definition and address this in a separate PR. We can move the deprecation warning and the type definition into the util package object (see f61bdddf7051522363e1d203fcd46b512047c87d), but then we fail tests using Counter with a `ScalaReflectionException` in Aggregate.scala:779 (in def cloneType) when: `Some(mirror.reflect(this).symbol)` generates `type Counter is not a class`. * Made @ducky64 change to Counter doc Used to generate an inline (logic directly in the containing Module, no internal Module is created) hardware counter.
2019-06-03Merge pull request #1004 from freechipsproject/chisel-stageChick Markley
Chisel stage
2019-05-22Make Driver a ChiselStage compatibility layerSchuyler Eldridge
This converts the original chisel3.Driver to use chisel3.stage.ChiselStage. This is implemented in the following way: 1. ExecutionOptions are converted to an AnnotationSeq 2. The AnnotationSeq is preprocessed using phases contained in the Chisel DriverCompatibility objects. One of these *disables* the execution of FirrtlStage by ChiselStage. 3. ChiselStage runs on the preprocessed AnnotationSeq 4. The input ExecutionOptionsManager is mutated based on the output of ChiselStage. 5. The FIRRTL stage is re-enabled if it's supposed to run and selected FIRRTL DriverCompatibility phases run. 6. FirrtlStage runs 7. The output AnnotationSeq is "viewed" as a ChiselExecutionResult This modifies the original DriverSpec to make it more verbose with the addition of info statements. The functionality of the DriverSpec is unmodified. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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