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2016-07-25catch Bad connection exceptionJim Lawson
2016-07-21Introduce chiselCloneType to distinguish from cloneType.Jim Lawson
Still fails one test - DirectionSpec in Direction.scala
2016-07-21Ensure test_wire is sinkable.Jim Lawson
2016-07-20More literal/width rangling.Jim Lawson
2016-07-20Distinguish between ?Int.Lit and ?Int.widthJim Lawson
2016-07-20Compile ok.Jim Lawson
Need to convert UInt(x) into UInt.Lit(x) or UInt.width(x)
2016-07-19Fixes for only connectwrap version.Jim Lawson
2016-07-19Merge in "complete" versions of Mem, Reg.Jim Lawson
2016-07-19Fix LitBinding and MultiAssign tests.Jim Lawson
2016-07-19Remove explicit literal binding.Jim Lawson
2016-07-19Incorporate connection logic.Jim Lawson
Compiles but fails tests.
2016-07-19Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3Jim Lawson
2016-07-18Update Chisel -> chisel3 references.Jim Lawson
2016-07-18Rename "Chisel" to "chisel3" (only git mv).Jim Lawson
2016-06-21Most of the remaining tests with Module, IO wrapping.Jim Lawson
2016-06-21New Module, IO, Input/Output wrapping.Jim Lawson
2016-06-08For Module instances we haven't named, suggest the Module class nameAndrew Waterman
2016-06-06Merge pull request #211 from ucb-bar/front_end_dependencyJim Lawson
Move more publishing definitions into commonSettings.
2016-06-06Move more publishing definitions into commonSettings.Jim Lawson
This should have been part of PR #194.
2016-06-03Merge pull request #194 from ucb-bar/front_end_dependencyJim Lawson
Add a hack to build.sbt to allow local publishing We're merging this despite the failing tests (Jenkins ghprb isn't communicating with GitHub following security and authentication updates). We'd prefer to package all the sbt subprojects in a single jar, but current attempts to do so fail. See #208.
2016-06-03Update publishing dependenciesJim Lawson
Until we sort out how to include the subproject classes in a single jar file, we need to explicitly publish all subprojects.
2016-06-03Merge branch 'master' into front_end_dependencyJim Lawson
2016-06-01Fix a fairly serious bug whereby Vec's could incorrectly compare as equal (#204)Wesley W. Terpstra
* chiselTests: include an example of two empty Vectors killing FIRRTL * Aggregate: fix a bug whereby Vec[T] was using equals/hashCode of Seq In Chisel, two vectors are NOT equal just if their contents are equal. For example, two empty vectors should not be considered equal. This patch makes Vec use the HasId._id for equality like other Chisel types. Without this fix, Bundle.namedElts.seen: HashSet[Data]() will eliminate one of the named vectors and emit bad IR.
2016-05-31Remove unsafe implicit conversions from BitPatducky
2016-05-31Move BitPat out of core/frontend, add implicit conversionDucky
2016-05-26Fix type constraint on PriorityMuxAndrew Waterman
2016-05-20Merge pull request #186 from ucb-bar/sloc_implRichard Lin
Source locators
2016-05-20Implementation of source locatorsducky
2016-05-20Update BackendCompilationUtilities.verilogToCpp to specify top-modulejackkoenig
This prevents Verilator from erroring when it cannot determine the top-module. It also changes the PRINTF_COND guard to correctly use the top-level reset instead of just the top of the Chisel-generated code.
2016-05-18Add a hack to build.sbt to allow local publishingchick
2016-05-13Merge pull request #191 from ucb-bar/classic_tester_prep_alt2Jim Lawson
remove Tester.scala
2016-05-12remove Tester.scala because chiselMain is now implemented in the ↵Danny
chisel-testers repo
2016-05-11Merge pull request #184 from ucb-bar/fix-regnextColin Schmidt
RegNext and RegInit should match Reg(next=) and Reg(init=)
2016-05-11RegNext and RegInit should match Reg(next=) and Reg(init=)Andrew Waterman
2016-05-10Some -> OptionDonggyu Kim
Option(null) returns None, but Some(null) returns Some(null)
2016-05-10Merge pull request #181 from ucb-bar/emitRefactorJim Lawson
Move emit out of IR
2016-05-10Move emit out of IRducky
2016-05-10Have Bits.toBools return Seq, not VecAndrew Waterman
The return value of Bits.toBools doesn't need to be dynamically indexed (as you could have just dynamically indexed the Bits itself), so returning a Seq instead of a Vec is mroe appropriate. This breaks a circular dependence between Bits and Vec, which helps with macros/frontend refactoring.
2016-05-10Relax Mem write-masks to Seq, rather than VecAndrew Waterman
2016-05-10Merge pull request #178 from ucb-bar/cfr_fixJim Lawson
Include Chisel Frontend in JAR
2016-05-09Include Chisel Frontend in JARducky
2016-05-09remove vpi source filesDonggyu Kim
2016-05-09fix width inference in enumDonggyu Kim
2016-05-09get -> getOrElseDonggyu Kim
2016-05-08Fixed sbt error where the typechecker was complaining. Just converted the ↵azidar
Seq to variatic argument list
2016-05-05Move Chisel API into separate chiselFrontend compilation unit in preparation ↵ducky
for source locator macros
2016-05-04Multiple assign testerducky
Closes #90
2016-05-04Remove dependences from Chisel core on Chisel utilsAndrew Waterman
Partially resolves #164
2016-05-04Support writing literals like 1.U or -1.SAndrew Waterman
2016-05-04clock|reset to _clock|_reset, added explanatory commentStephen Twigg
@aswaterman closes #156