summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2021-02-11Fix stack trace trimming across Driver/ChiselStage (#1771)Schuyler Eldridge
* Handle MemTypeBinding in Analog Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Fix stack trace trimming across ChiselStage Fix bug in stack trace trimming behavior. Now, the following is what happens: 1. The Builder, if catching accumulated errors, will now throw a ChiselException with a Scala-trimmed Stack trace. Previously, this would throw the full excpetion. 2. The Elaborate phase handles stack trace trimming. By default, any Throwable thrown during elaboration will have its stack trace *mutably* trimmed and is rethrown. A logger.error is printed stating that there was an error during elaboration and how the user can turn on the full stack trace. If the --full-stacktrace option is on, then the Throwable is not caught and only the first logger.error (saying that elaboration failed) will be printed. 3. ChiselStage (the class), ChiselStage$ (the object), and ChiselMain all inherit the behavior of (2). Mutable stack trace trimming behavior is moved into an implicit class (previously this was defined on ChiselException only) so this can be applied to any Throwable. No StageErrors are now thrown anymore. However, StageErrors may still be caught by ChiselMain (since it is a StageMain). Testing is added for ChiselMain, ChiselStage, and ChiselStage$ to test all this behavior. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-02-10Merge pull request #1624 from chipsalliance/gc-dataJack Koenig
Make Data GC-able
2021-02-09Make it possible to GC Data instancesJack Koenig
No longer create a pointer from parent to every HasId, only do it by default for BaseModules and MemBases. Add pointer from parent to Data upon binding the Data. * Add MemTypeBinding for port types of Mems This binding is similar to the SampleElementBinding for Vecs in that these Data are not truly hardware, but are represented in the FIRRTL IR and thus need some representation. * Call _onModuleClose on unbound Records This maintains some corner-case behavior that is nevertheless relied upon. It ensures that refs are set for the elements of Records, even if they are not bound to any real hardware.
2021-02-09Add no-plugin-tests for testing Chisel without the compiler pluginJack Koenig
This is a new SBT build unit that symlinks in some files from the normal chisel project tests, but builds them without the compiler plugin.
2021-02-08Parametrized Mem- & SyncReadMem-based implementation of the Queue class (#1740)Vladimir Milovanović
* Added SyncReadMem-based implementation of the Queue class * Rework of the parametrized Queue class SyncReadMem-based implementation * Modification of the parametrized Queue class SyncReadMem-based implementation * Limiting the visibility of the read address for SyncReadMem-based Queue Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-02-05Add file line to source link from scaladoc (#1776)John's Brew
Signed-off-by: Jean Bruant <jean.bruant@ovhcloud.com>
2021-02-04Minor docs improvements (#1774)Jack Koenig
* Fix some botched formatting (replace ```mdoc scala with ```scala mdoc) * Replace some unnecessary uses of triple backticks with single backticks * Move appendix docs from wiki-deprecated/ to appendix/ * This will require an update on the website as well * Update Bundle literal docs
2021-02-03Remove Deprecated APIs (#1730)Jiuyang Liu
2021-02-01Update reported width from div/rem to match FIRRTL results (#1748)Albert Magyar
* Update reported width from div/rem to match FIRRTL results * Add tests for width of % and / on UInt and SInt * Add loop-based test for known UInt/SInt op result widths Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-02-01Bump to Scala 2.12.13 (#1766)Jack Koenig
2021-01-27Fix some typo and using foreach instead of map in BoringUtils (#1755)SoyaOhnishi
If a method passed to higher function does not return any value, it is prefer to use `foreach` instead of `map`. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-01-27Fix incorrect comment in ScalaDoc (#1756)Jack Koenig
2021-01-24Refactor EnumAnnotations and EnumFactory (#1747)SoyaOhnishi
This is a nit fix. no logic is changed. * Rename `typeName` to `enumTypeName` in ScalaDoc * Add return type at public method * Rename `enum_records` into `enumRecords` to retain name consistency Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-01-22Add redirect for Scala 2.11 upgrade page (#1749)Jack Koenig
2021-01-21Merge pull request #1745 from chipsalliance/remove-val-ioJack Koenig
Remove "val io" and rename MultiIOModule to Module
2021-01-21Apply suggestions from code reviewJack Koenig
Co-authored-by: Megan Wachs <megan@sifive.com>
2021-01-21Update docs for the removal of val io and MultiIOModuleJack Koenig
2021-01-21Fold Chisel.CompatibilityModule into chisel3.internal.LegacyModuleJack Koenig
2021-01-21Remove val ioJack Koenig
Chisel projects no longer need -Xsource:2.11 when compiling with Scala 2.12. Autowrapping of "val io" for compatibility mode Modules is now implemented using reflection instead of calling the virtual method. Also move Chisel.BlackBox to new chisel3.internal.LegacyBlackBox
2021-01-21Deprecate override_clock and override_reset in ModuleJack Koenig
2021-01-21Rename MultiIOModule to ModuleJack Koenig
2021-01-20remove 2.11 dedicated code. (#1744)Jiuyang Liu
This PR revert #1480, but keep the test. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-01-20Fix Mergify condition for labeling backports (#1742)Jack Koenig
2021-01-19Add when.cond for getting the current when condition (#1694)Jack Koenig
This is useful for libraries to guard operations implemented via annotations or BlackBoxes by the current when predicate
2021-01-15Merge pull request #1732 from chipsalliance/farewell_scala_211Jack Koenig
Farewell Scala 2.11
2021-01-15farewell Scala 2.11Jiuyang liu
2021-01-11Make `toTarget` fail if called on a Literal (or would otherwise not ↵Megan Wachs
serialize properly) (#1714) * Add (failing) Test for Data toTarget calls Add scaladoc and clean up test * Builder: don't let .toTarget pass if it won't be able to deserialize properly later * Update src/test/scala/chiselTests/ReferenceTargetSpec.scala * Rename and simplify tests for literal toTarget
2021-01-06Update meeting url (#1716)Jiuyang Liu
2020-12-17Automate publishing of SNAPSHOTS with sbt-ci-release (#1706)Jack Koenig
2020-12-17Remove CircleCI (#1702)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-12-17Bump SNAPSHOT and SNAPSHOT dependencies (#1701)Jack Koenig
2020-12-16Switch to using Github Actions CI (#1690)Jack Koenig
MiMa binary compatibility checks are now run on master, but the mimaPreviousArtifacts are empty which makes the check a no-op. This helps keep both the build.sbt and CI more consistent between master and stable branches. .mergify.yml is also updated with mergify.sc from chisel-repo-tools using the following configuration: conditions: - status-success=all tests passed branches: - 3.2.x - 3.3.x - 3.4.x
2020-12-08Make Maven show chisel3 as apache-2.0 (#1695)Chick Markley
- fix build.sbt - fix build.sc
2020-12-07(encore) Builder: use LazyLogging.logger.warn to print elaboration message ↵Jiuyang Liu
(#1670) * Builder: use LazyLogging.logger.warn to print elaboration message * add deprecation for chisel3.internal.ErrorLog.info. * add test to check elaboration message still exist. Co-authored-by: Kevin Laeufer <kevin.laeufer@sifive.com>
2020-12-01Fix RegInit of Bundle lits (#1688)Jack Koenig
Implemented by folding Element.ref into Data.ref. Element.ref had special handling for literals, but because Bundles can also be literals, there were code paths that tried to get the ref of a Bundle literal which was non-existent. Now, all literals are handled together. Because FIRRTL does not have support for Bundle literals, Bundle literal refs are implemented by materializing a Wire.
2020-12-02readme: simplify sbt snippet and update to the latest stable release (#1686)Kevin Laeufer
2020-11-24Update some README links to chipsalliance (#1673)Jack Koenig
2020-11-16Improve source locators for switch statements. (#1669)Daniel Kasza
* Improve source locators for switch statements.
2020-11-11Add custom mdoc modifier for emitted Verilog (#1666)Jack Koenig
2020-11-11Ignore tests using System.setSecurityManager (#1661)Jack Koenig
The SecurityManager is global so is not thread-safe. This is the source of flaky tests in FIRRTL CI. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-11Refine autonaming to have more intuitive behavior (#1660)Jack Koenig
* Refine autonaming to have more intuitive behavior Last name in an Expression wins, while the first Statement to name wins. This is done via checking the _id of HasIds during autonaming and only applying a name if the HasId was created in the scope of autonaming. There is no change to .autoSeed or .suggestName behavior. Behavior of chisel3-plugins from before this change is maintained. * Update docs with naming plugin changes
2020-11-05For HasId.setRef, have first set win (with force override) (#1655)Jack Koenig
This is a refinement of the assertion added in #1616 then removed in #1654. Because Records now set the refs of children upon binding, later, unbound Records could incorrectly override the refs. The first set should win.
2020-11-03Remove Data.setRef assertion (#1654)Jack Koenig
It causes issues for some legal (if awkward) patterns. A larger refactor of when refs are set could reinstate this check.
2020-11-02SeqUtils asUInt endian-ness: hi/lo instead of right/left (#1647)John Ingalls
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-02Bugfix - adding external modules was broken (#1649)Adam Izraelevitz
2020-10-30Fix bug where refs may not get set for Records (#1645)Jack Koenig
This requires a combination of things, but it happens to be a combination used by Diplomacy in Rocket Chip. It must be a Record in compatibility code with Vecs as fields and a mix of components with and without set directions.
2020-10-27Fix broken links in docs (#1643)Adam Izraelevitz
2020-10-26Fix crosslinks in mdoc. Can't use md suffix (#1640)Adam Izraelevitz
* Fix crosslinks in mdoc. Can't use md suffix * Removed all .md crossrefs Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-10-26Bugfix - module name collision for injecting aspect (#1635)Adam Izraelevitz
* Bugfix - module name collision for injecting aspect * Fixed mechanism to avoid module name collisions * Added comments for reviewer feedback Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-10-26Added Force Name API (#1634)Adam Izraelevitz
* Added forcename transform and tests * Added documentation and additional error checking * Added mdoc. Added RunFirrtlTransform trait * Removed TODO comment * Addressed reviewer feedback * Removed trailing comma Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-13 18:09:13 +0000