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2021-05-11Update sbt to 1.3.13 (#1501)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-11Update scalacheck-1-14, ... to 3.1.4.0 (#1575)Scala Steward
* Update scalacheck-1-14, ... to 3.1.4.0 * Update scalacheck-1-14, ... to 3.1.4.0 * Update scalacheck-1-14 to 3.1.4.0 Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-11Update sbt-scoverage to 1.8.0 (#1905)Scala Steward
2021-05-10implement equal to BitPat. (#1867)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-09Fix ShiftRegister with 0 delay. (#1903)Jiuyang Liu
* Add test to check ShiftRegister(s) with delay is 0. This should break ShiftRegister(x, 0) since last is not exist in a empty Seq. Originally, test only test 1 to 4, which missed a potential bug from #1723. * Fix ShiftRegister with 0 delay. if ShiftRegisters is empty, java will complain: ``` java.util.NoSuchElementException scala.collection.LinearSeqOptimized.last(LinearSeqOptimized.scala:150) ``` This fix this issue and return `in` directly when ShiftRegister size is 0. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-07Update sbt-mima-plugin to 0.9.0 (#1900)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2021-05-06add ShiftRegisters to expose register inside ShiftRegister. (#1723)Jiuyang Liu
* add ShiftRegisters to expose register inside ShiftRegister. * use Seq.iter for oneline implementation.
2021-05-05Remove chisel3.stage.phases.DriverCompatibility (#1772)Schuyler Eldridge
2021-05-04Update sbt-scoverage to 1.7.3 (#1899)Scala Steward
2021-04-30add helper function to convert chirrtl to firrtl. (#1854)Jiuyang Liu
* add convert(chirrtl: cir.Circuit): fir.Circuit to convert chirrtl to firrtl. * add scaladoc. * add test. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-29Scala 2.13 support (#1751)Jack Koenig
2021-04-29verification: guard statements with module reset (#1891)Kevin Laeufer
2021-04-29Update sbt-ci-release to 1.5.7 (#1832)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-29Update sbt-mdoc to 2.2.20 (#1870)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-29Update sbt-scalafix to 0.9.27 (#1842)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-29Update scopt to 4.0.1 (#1815)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-29Update sbt-scoverage to 1.7.0 (#1887)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-28Cookbook: clean up desiredName example (#1886)Megan Wachs
* Cookbook: clean up desiredName example * Update cookbook.md
2021-04-27Introduce VecLiterals (#1834)Chick Markley
This PR provides for support for Vec literals. They can be one of two forms Inferred: ``` Vec.Lit(0x1.U, 0x2.U) ``` or explicit: ``` Vec(2, UInt(4.W)).Lit(0 -> 0x1.U, 1 -> 0x2.U) ``` - Explicit form allows for partial, or sparse, literals. - Vec literals can be used as Register initializers - Arbitrary nesting (consistent with type constraints is allowed)
2021-04-26Cookbooks: make examples more clear and remove naming (#1881)Megan Wachs
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-26Add some error context to Converter .getRefs (#1878)Jack Koenig
2021-04-26Fix Gitter link in README (#1879)Jack Koenig
2021-04-21fixing context bug (#1874)Deborah Soung
2021-04-21Add a link to the Chisel book (#1872)Martin Schoeberl
2021-04-19Update polymorphism-and-parameterization.md (#1868)Fabien Marteau
nitpick
2021-04-15update CCC2021 info (#1861)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-15Improve Mergify labeling of backports (#1865)Jack Koenig
Using https://github.com/ucb-bar/chisel-repo-tools/pull/31
2021-04-14Fix doc formatting and generation (#1863)Carlos Eduardo
* Remove space between backticks and language * Make code examples in memories explanation work Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-04-12Add "how to tie off to 0" to the Cookbook (#1857)Megan Wachs
2021-04-07Update PULL_REQUEST_TEMPLATE.md (#1856)Megan Wachs
2021-04-07Add documentation guide about memory initialization (#1850)Carlos Eduardo
* Add documentation guide about memory initialization * Move information to experimental and add ref
2021-04-01Fix Gitter chat room link (#1848)XinJun Ma
2021-03-31Fix formatting issue of links (#1844)Kalamár Ödön
2021-03-29Provide useful message on Vec.apply require (#1838)Jack Koenig
2021-03-27CCC 2021 placeholder (#1794)Jiuyang Liu
* Add CCC2021 info * Update README.md * Update README.md
2021-03-23Make plugin autoclonetype always on (#1826)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-03-18Update the FAQ and add doc on versioning (#1827)Jack Koenig
* Update the FAQ and add doc on versioning * Update modules.md Co-authored-by: Megan Wachs <megan@sifive.com>
2021-03-18Reorganize website docs (#1806)Megan Wachs
Updates to chisel3 documentation for website: * guard code examples with mdoc and fix errors encountered along the way * move some website content here vs splitting the content across two repos * Bring in the interval-types and loading memories content so that it will be visible from the website * remove all references to the wiki (deprecated) * Remove reference to Wiki from the README * fix tabbing and compile of chisel3-vs-chisel2 section * Appendix: faqs now guarded and compile * FAQs: move to resources section
2021-03-18Add toString method to BitPat (#1819)Boyang Han
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-03-18Don't toggle top.cpp clock and reset on same cycle (#1820)Schuyler Eldridge
Change top.cpp to deassert reset one time unit before the clock asserts. This avoids a Verilator simultation issue in top.cpp where the eval() function is only called once per simultation loop. If the clock and reset are both changed and eval() is only called once, then any combinational update due to a change in reset is not visible to the sequential logic. This avoids issues where the downstream compilation utilities move synchronous reset logic outside of an always block that describes a synchronous reset flip flop. Reset now deasserts on time unit 10 and the clock ticks on time unit 11. h/t @albert-magyar Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-03-17Fix incorrect usage of emitFirrtl in test (#1817)Schuyler Eldridge
Change a test to use emitChirrtl instead of emitFirrtl. This test isn't supposed to be running the Scala FIRRTL Compiler, but the latter method causes this to happen. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-03-15allowReflectiveAutoCloneType must work outside of Builder context (#1811)Jack Koenig
2021-03-12Merge pull request #1804 from chipsalliance/autoclonetype2Jack Koenig
Compiler plugin implemented autoclonetype
2021-03-12[plugin] Disable BundleComponent by default, add option to enableJack Koenig
2021-03-12[plugin] Stop autoclonetype stack traces when using pluginJack Koenig
The compiler plugin obviates the need for using stack traces to determine outer objects in autoclonetype. When the plugin was used to compile a given Bundle, it will no longer collect a stack trace upon construction. This should have massive benefits to elaboration runtime.
2021-03-12[plugin] Implement autoclonetype in the compiler pluginJack Koenig
2021-03-11[plugin] Split ChiselComponent into its own fileJack Koenig
2021-03-11Import memory files inline for Verilog generation (#1805)Carlos Eduardo
This annotation adds memory import with inline generation for the emmiter. Supports both readmemh and readmemb statements based on argument.
2021-03-03Add header for chisel-enum.md (#1800)Jack Koenig
2021-03-02Adding ChiselEnum Documentation Entry (#1795)chrisbaldwin2
* Adding ChiselEnum Documentation Entry Added documentation for the ChiselEnum type with verified examples * Fixed some doc ambiguity and repeated emitVerilog calls * Added ChiselStage and commented out package definition since packages cannot be declared in single files * Fixed issue with ChiselStage not being able to generate a module with parameters and bad package imports * Opps on not adding _ after import * Update docs/src/explanations/chisel-enum.md Co-authored-by: Megan Wachs <megan@sifive.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by: Megan Wachs <megan@sifive.com> * Modified Bundle for ci and made changes to select naming scheme * Update docs/src/explanations/chisel-enum.md Co-authored-by: Megan Wachs <megan@sifive.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by: Megan Wachs <megan@sifive.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by: Megan Wachs <megan@sifive.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by: Megan Wachs <megan@sifive.com> * Added missing backticks * Added space around error block quote * Fixed md paragraph in code * Update docs/src/explanations/chisel-enum.md Co-authored-by: Megan Wachs <megan@sifive.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com> * Update docs/src/explanations/chisel-enum.md Co-authored-by: Megan Wachs <megan@sifive.com> * Fixed some comments and formatting Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
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