| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-09-16 | Merge branch 'master' into gsdt | Jim Lawson | |
| o explain why this merge is necessary, | |||
| 2016-09-16 | Rename DecoupledIO object to Decoupled (compatibility). | Jim Lawson | |
| 2016-09-15 | Decoupled: cast DecoupledIO to IrrevocableIO as an input (#280) | Wesley W. Terpstra | |
| 2016-09-15 | add optional directionality assumption to BiConnect.elemConnect | Jim Lawson | |
| 2016-09-15 | move AddMethodsToDecoupled to ReadyValid | Jim Lawson | |
| 2016-09-15 | Revert "Add direction-only (no width) UInt factory method." | Jim Lawson | |
| This reverts commit 920f6dc168d8e486733666368c7e363065b685ee. | |||
| 2016-09-15 | Add direction-only (no width) UInt factory method. | Jim Lawson | |
| 2016-09-15 | Merge branch 'master' into gsdt | Jim Lawson | |
| 2016-09-13 | Bugfix: actually pass flow parameter from Queue factory to Queue module ↵ | Henry Cook | |
| constructor | |||
| 2016-09-09 | Convert to NotStrict for internal connection checks. | Jim Lawson | |
| 2016-09-08 | Add IrrevocableIO alternative to DecoupledIO (#274) | Henry Cook | |
| Add IrrevocableIO subclass of DecoupledIO that promises not to change .bits on a cycle after .valid is high and .ready is low | |||
| 2016-09-08 | Merge pull request #275 from ucb-bar/fix-printable | Jim Lawson | |
| Fix bug in Printable FullName of submodule port | |||
| 2016-09-07 | Fix bug in Printable FullName of submodule port | jackkoenig | |
| Printable was using HasId.instanceName to get full names of Chisel nodes. instanceName uses the parent module of the HasId to get the Component to use in calling fullName on the underlying Ref. Unfortunately this means that any reference to a port of a instance will leave off the instance name. Fixing this required the following: - Add Component argument to Printable.unpack so that we can call Arg.fullName directly in the Printable - Pass the currently emitting module as the Component to Printable.unpack in the Emitter - Remove ability to create FullName Printables from Modules since the Module name is not known until after the printf is already emitted This commit also updates the PrintableSpec test to check that FullName and Decimal printing work on ports of instances | |||
| 2016-09-07 | Add Printable (#270) | Jack Koenig | |
| Printable is a new type that changes how printing of Chisel types is represented It uses an ordered collection rather than a format string and specifiers Features: - Custom String Interpolator for Scala-like printf - String-like manipulation of "hardware strings" for custom pretty-printing - Default pretty-printing for Chisel data types | |||
| 2016-09-06 | Verify we can suppress the inclusion of default compileOptions. | Jim Lawson | |
| 2016-09-02 | Rename implicit compileOptions to defaultCompileOptions. | Jim Lawson | |
| 2016-09-02 | Add/cleanup UInt/SInt factory methods. | Jim Lawson | |
| 2016-09-02 | Deprecate asBits; modify deprecation warnings accordingly | Andrew Waterman | |
| 2016-09-01 | Remove O(n^2) code in Vec.apply(Seq) | Andrew Waterman | |
| The O(n) type legality check was redundantly executed n times. D'oh. | |||
| 2016-09-01 | Merge pull request #273 from ucb-bar/check-vec | Jim Lawson | |
| Check that Vecs have homogeneous types | |||
| 2016-09-01 | Deprecate Vec.fill() offering Vec(Seq.fill()). | Jim Lawson | |
| 2016-09-01 | Move connection implicits from Module constructor to connection methods. | Jim Lawson | |
| Eliminate builder compileOptions. | |||
| 2016-09-01 | Bump version number in preparation for release. | Jim Lawson | |
| 2016-08-31 | Check that Vecs have homogeneous types | Andrew Waterman | |
| Vec[Element] can have heterogeneous widths. Vec[Aggregate] cannot (but possibly could relax this by stripping widths from constituent Elements and relying on width inference). | |||
| 2016-08-31 | Bump version number in preparation for release. | Jim Lawson | |
| 2016-08-30 | Merge branch 'master' into gsdt | Jim Lawson | |
| 2016-08-30 | Make compileOptions in the Chisel package effective. | Jim Lawson | |
| Remove references to the Chisel package in favor of explicit chisel3 imports in tests, | |||
| 2016-08-30 | Explicitly clone the target type in noenq() to avoid "already bound" errors ↵ | Jim Lawson | |
| for io ports. | |||
| 2016-08-30 | Add example of specific CompileOptions settings to tests. | Jim Lawson | |
| 2016-08-30 | Use correct case for Strict/NotStrict compile options. | Jim Lawson | |
| 2016-08-30 | Add abstract classes with explicit connection checking options. | Jim Lawson | |
| 2016-08-30 | Allow compileOptions as optional arguments to elaborate() and emit(). | Jim Lawson | |
| 2016-08-30 | Correct parameter name (topModule) in ScalaDoc. | Jim Lawson | |
| 2016-08-29 | Check module-specific compile options. | Jim Lawson | |
| Import chisel3.NotStrict.CompileOptions in Chisel package. Add CompileOptions tests. | |||
| 2016-08-29 | Rename CompileOptions implicit objects. | Jim Lawson | |
| 2016-08-29 | Pass compileOptions as an implicit Module parameter. | Jim Lawson | |
| 2016-08-29 | Rename individual compile options. | Jim Lawson | |
| Stricter values are "true". Current default (not strict) values are "false". | |||
| 2016-08-26 | Merge pull request #259 from ucb-bar/addpublicnode | Chick Markley | |
| Public APIs for chisel object names | |||
| 2016-08-25 | fix a bug in setModName | Donggyu Kim | |
| 2016-08-25 | Use bulkConnect in Vec,fill if any (flattened) element of the Vec has a ↵ | Jim Lawson | |
| direction associated with it. This impetus for this came out of discussion during the chisel meeting of 8/24/16 in response to errors running the chisel tutorial examples Adder test. | |||
| 2016-08-24 | Per Chisel meeting. | chick | |
| signalName -> instanceName SignalId -> InstanceId Based on Stephen's comments on PR | |||
| 2016-08-23 | Swap name of compileOption "assumeNoDirectionIsOutput" to ↵ | Jim Lawson | |
| "assumeNoDirectionIsInput". | |||
| 2016-08-22 | Purely cosmetic changes to placate the scalastyle checker. | Jim Lawson | |
| 2016-08-22 | Fix firrtlDirection for class DeqIO. | Jim Lawson | |
| 2016-08-21 | AnnotatingExample: | chick | |
| Removed extraneous logic Renamed doStuff to buildAnnotatedCircuit Removed println's | |||
| 2016-08-21 | Add AnnotationSpec file which provides an example of a way to implement ↵ | chick | |
| generation of annotations in a chisel circuit that could be used by custom firrtl passes This spec also shows and tests in a limited way the new API of .signalName, .pathName, parentModName which allows access to the various path information of a chisel component (something that subclasses SignalId, most prominently SubClasses of Data and Module | |||
| 2016-08-21 | Add annotating example to test new signal name api | chick | |
| 2016-08-21 | provides signal name methods for firrtl annotation and chisel testers | Donggyu Kim | |
| * signalName: returns the chirrtl name of the signal * pathName: returns the full path name of the signal from the top module * parentPathName: returns the full path of the signal's parent module instance from the top module * parentModName: returns the signal's parent **module(not instance)** name. | |||
| 2016-08-19 | Restore immutability of direction overrides. | Jim Lawson | |
| Input, Output, and Flipped clone their inputs. | |||
| 2016-08-19 | Simplify autioIOWrap code in computePorts(). | Jim Lawson | |
| As a side-effect, handle BlackBoxes correctly. | |||
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index : chiselX | |
| Chisel with SFC compatibility |
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