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Fix bug in Printable FullName of submodule port
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Printable was using HasId.instanceName to get full names of Chisel nodes.
instanceName uses the parent module of the HasId to get the Component to use in
calling fullName on the underlying Ref. Unfortunately this means that any
reference to a port of a instance will leave off the instance name. Fixing this
required the following:
- Add Component argument to Printable.unpack so that we can call Arg.fullName
directly in the Printable
- Pass the currently emitting module as the Component to Printable.unpack in
the Emitter
- Remove ability to create FullName Printables from Modules since the Module
name is not known until after the printf is already emitted
This commit also updates the PrintableSpec test to check that FullName and
Decimal printing work on ports of instances
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Printable is a new type that changes how printing of Chisel types is represented
It uses an ordered collection rather than a format string and specifiers
Features:
- Custom String Interpolator for Scala-like printf
- String-like manipulation of "hardware strings" for custom pretty-printing
- Default pretty-printing for Chisel data types
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The O(n) type legality check was redundantly executed n times. D'oh.
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Check that Vecs have homogeneous types
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Vec[Element] can have heterogeneous widths.
Vec[Aggregate] cannot (but possibly could relax this by stripping widths
from constituent Elements and relying on width inference).
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Public APIs for chisel object names
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signalName -> instanceName
SignalId -> InstanceId
Based on Stephen's comments on PR
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Removed extraneous logic
Renamed doStuff to buildAnnotatedCircuit
Removed println's
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generation of annotations in a chisel circuit that could be used by custom firrtl passes
This spec also shows and tests in a limited way the new API of .signalName, .pathName, parentModName which allows access to the various path information of a chisel component (something that subclasses SignalId, most prominently SubClasses of Data and Module
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* signalName: returns the chirrtl name of the signal
* pathName: returns the full path name of the signal from the top module
* parentPathName: returns the full path of the signal's parent module instance from the top module
* parentModName: returns the signal's parent **module(not instance)** name.
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* Make "def width" a private API; expose isWidthKnown instead
Resolves #256.
Since width was used to determine whether getWidth would succeed, I added
def isWidthKnown: Boolean
but another option would be to expose something like
def widthOption: Option[Int]
...thoughts?
* Document getWidth/isWidthKnown
* Add widthOption for more idiomatic Scala manipulation of widths
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The API allowed this before, but not safely, as users could create
name conflicts. This exposes the pre-deduplication/sanitization
naming API, and closes the other one.
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It's not entirely clear what the FIRRTL implementation supports, so
I'm using the ANSI C requirements for the time being.
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This has been deprecated for a long time now (and really shouldn't
have existed to begin with).
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Deprecating toBits removes the capability to cast an arbitrary
type to UInt. While it's still possible to do so using asBits.asUInt,
this creates boilerplate. (asBits is almost never useful itself.)
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For Chisel nodes defined in Module class-level values of type Option or
Iterable, we can still use reflection to assign names based on the name
of the value. This works for arbitrary nesting of Option and Iterable so
long as the innermost type is HasId. Note that this excludes Maps which
always have an innermost type of Tuple2[_,_].
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Clean up Scala code, and use +& to generate a lot less FIRRTL
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For reasonable circuit delay, need to divide & conquer.
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Closes #229
h/t @sdtwigg @davidbiancolin
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renamechisel3 - "chisel" -> "chisel3"
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(#223)
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Rather than using a global counter, memoize the last returned value for
colliding names to generate smaller sequence numbers.
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Rename package Chisel to chisel, add Chisel package for compatibility
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package/folder, move more things into utils
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