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2017-04-07Change Enum to emit minimum widths of 1 (#574)Jack Koenig
Fixes #554
2017-04-04Use input element to decide if Vec of values has direction (#570)Jack Koenig
Using the sample_element of the created wire is incorrect because Wires have no direction so the Wire constructed for a Vec of Module IO was constructed incorrectly. Fixes #569 and resolves #522.
2017-04-04Define CompileOptions case class to support CompileOptions manipulation. (#572)Jim Lawson
Make it relatively easy to override a single CompileOption.
2017-04-02Make Module instantiations draw clock from Builder instead of parent (#568)Jack Koenig
Fixes #567
2017-04-02Merge pull request #564 from ucb-bar/bugfix-lost-width-on-fixed-literalsgrebe
Creating FixedPoint literals was throwing away width
2017-03-28Creating FixedPoint literals was throwing away width when specifically provided.chick
This caused one hot muxing problems in dsptools FixedPoint spec fixed based on error uncovered by this change
2017-03-27Support Vec(0) fields in Bundles, just like Option[Data]; add testAndrew Waterman
This also allows asUInt/asTypeOf to work properly on those Bundles, even though zero-width wire support is lacking.
2017-03-24Fix getWidth on empty Vecs; add testAndrew Waterman
Use fold(0) instead of reduce to handle the corner case.
2017-03-24Fixed fix, allow Mux of different binary points and widths (#559)Richard Lin
Allow muxing FxP of different widths and BPs
2017-03-17Add single arg constructor back to compatibility reg (#553)Richard Lin
2017-03-13Revert "Change Vec creation to check if gen is lit (and hence needs t… (#530)Jim Lawson
* Revert "Change Vec creation to check if gen is lit (and hence needs to be declared)" This reverts commit dc86e7e1734d6abacb739b488df1de231e6b41b2. This may address #522 - using chiselCloneType (instead of cloneType) to preserve directionality. * Add missing implicits to Vec.apply() signature. * Use correct macro (CompileOptionsTransform) for indexWhere.
2017-03-08Deprecate old Reg with nulls constructor (#455)Richard Lin
2017-03-08Move log2Up and log2Down to compatibility wrapperAndrew Waterman
2017-03-08Avoid log2Up in testsAndrew Waterman
2017-03-08Avoid log2Up in ShiftRegisterTesterAndrew Waterman
This is an odd one. Using log2Ceil directly results in a Verilator compile error, presumably due to a FIRRTL zero-width wire bug.
2017-03-08Improve UIntToOH behavior on incorrect inputs; avoid log2UpAndrew Waterman
The old implementation failed to check for width <= -2, and did the wrong thing when -1 was explicitly passed. Splitting into two methods avoids the latter issue. log2Ceil's argument might be 1, so employ a max operator.
2017-03-08In OHToUInt, use log2Ceil instead of log2UpAndrew Waterman
Since the argument is at least 2, this change has no semantic effect.
2017-03-08Use zero-width wire for 1-entry enumAndrew Waterman
2017-03-08In Counter, use log2Ceil instead of log2UpAndrew Waterman
Since the argument is at least 2, this change has no semantic effect.
2017-03-08Fix the widths of QueueIO.count and ArbiterIO.chosen for entries=0Andrew Waterman
Both should be zero-width wires.
2017-03-08Improve Reverse's exception behavior; avoid log2UpAndrew Waterman
Provide a better error message when length < 0. Change log2Up in log2Ceil, which has no effect, since the argument is always at least 2.
2017-03-08Correct Fill's exception behavior; avoid log2UpAndrew Waterman
It always should throw an exception when n < 0, but in the specific case of x.isWidthKnown && x.getWidth == 1, it failed to do so. This commit also changes log2Up in log2Ceil, which has no effect, since the argument is always at least 2.
2017-02-28Fix minor typo in readme (#537)Siddhanathan Shanmugam
2017-02-28Use test_run_dir for more tests. (#534)Jim Lawson
* Use test_run_dir for more tests. * Use official option and DRY. Make "test_run_dir" the default for ChiselSpec. Verify output files are created in DriverSpec tests.
2017-02-27Add test for digit field names in RecordsJack Koenig
2017-02-27Record: allow elements to start with a digitWesley W. Terpstra
This is necessary for user-defined Record-derived types to retain the same signal name as they would using a Vec.
2017-02-27Update BetterNamingTests to use NamedModuleTesterJack Koenig
2017-02-24Fix mismatch between Chisel and Firrtl on UInt -& UIntJack Koenig
Fixes #501. Also added UIntOps test.
2017-02-24Test that large Vecs can have widths inferredjackkoenig
Test for ucb-bar/firrtl#407
2017-02-24Escape % in assertion messagesJack Koenig
2017-02-23Fend off future bug - replace FixedPoint ":=" with "connect". (#516)Jim Lawson
This turned up after updating #494 (Remove explicit import of NotStrict) and adding the missing implicit CompileOptions to ":="'s signature at which point Scala pointed out FixedPoint's ":=" could not override Data's final ":=" with the same signature: the implicit time bomb.
2017-02-22Bugfix #513. Fix BPSet width inference in Chisel3 (#523)Adam Izraelevitz
* Bugfix #513. Needs better test case * Improved test
2017-02-21Use chisel3 in libraryDependencies example. (#520)Jim Lawson
2017-02-17Builderreflectionfix (#515)Angie Wang
* change builder for bundle reflection fix * fixed bug -- should be not assignable
2017-02-16Add scaladoc examples for Vec and Bundle (#511)Chick Markley
* Add scaladoc examples for Vec and Bundle * address comments, added @example tag eliminate extraneous context * address comments, added @example tag eliminate extraneous context * ok, I've wrestled with the javadoc sytnax, the following commit, is my best result so far
2017-02-16Add support for clock and reset scoping (#509)Jack Koenig
withClockAndReset, withReset, and withClock allow changing the implicit clock and reset. Module.clock and Module.reset provide access to the current implicit clock and reset.
2017-02-15Blackbox comments spelling correction thanks to edwardcwangFabien Marteau
2017-02-15BlackBox documentation: adding the verilog template to generateFabien Marteau
2017-02-15Adding a BlackBox example in code documentationFabien Marteau
2017-02-15Implement asTypeOf, refactor internal APIs (#450)Richard Lin
2017-02-15Fixed point factory stuff (#505)Chick Markley
* Don't allow analog to analog monoconnect adjust tests accordingly * demonstrate bit loss in shift right for fixed point * cleaned up some stuff. this does not test clean due to bug in firrtl
2017-02-08Fix random failures in CompatibilitySpec (#498)Jack Koenig
2017-02-08Add Analog typeJack Koenig
Used for stitching Verilog inout through Chisel Modules (from BlackBox to BlackBox)
2017-02-08Add counter for depth of when scopeJack Koenig
2017-02-08Fix up deprecation warnings and clean up CompatibiltySpec code. (#471)Jim Lawson
There was some dubious (certainly unclear) code organization in the CompatibiltySpec tests. The isPow2() test was randomly failing in Jenkins builds. This may address the problem.
2017-02-08Bump sbt version.Jim Lawson
2017-02-07Fix up Absolute value #abs (#491)Chick Markley
* Fix up Absolute value #abs Defines #abs in Num Implement #abs in UInt Change #abs in SInt to return an SInt Change #abs in FixedPoint to return a FixedPoint Added a couple of tests Add some scala style suppression to Bits so I can read code in IntelliJ * Per review Add tests that abs works for positive values Added SInt and UInt tests for abs to new underpopulated IntegerMathSpec Used fixed point literals in fixed points abs definition
2017-02-07Add generateFirrtl() method to ChiselSpec.scala (#423)Jim Lawson
2017-02-07Name all the thingsducky
2017-02-07Add macro for compile options materialize to prevent its use in chisel coreducky
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