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(#223)
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Rather than using a global counter, memoize the last returned value for
colliding names to generate smaller sequence numbers.
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Rename package Chisel to chisel, add Chisel package for compatibility
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package/folder, move more things into utils
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Move more publishing definitions into commonSettings.
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This should have been part of PR #194.
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Add a hack to build.sbt to allow local publishing
We're merging this despite the failing tests (Jenkins ghprb isn't communicating with GitHub following security and authentication updates). We'd prefer to package all the sbt subprojects in a single jar, but current attempts to do so fail. See #208.
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Until we sort out how to include the subproject classes in a single jar file, we need to explicitly publish all subprojects.
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* chiselTests: include an example of two empty Vectors killing FIRRTL
* Aggregate: fix a bug whereby Vec[T] was using equals/hashCode of Seq
In Chisel, two vectors are NOT equal just if their contents are equal.
For example, two empty vectors should not be considered equal. This
patch makes Vec use the HasId._id for equality like other Chisel types.
Without this fix, Bundle.namedElts.seen: HashSet[Data]() will eliminate
one of the named vectors and emit bad IR.
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Source locators
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This prevents Verilator from erroring when it cannot determine the top-module.
It also changes the PRINTF_COND guard to correctly use the top-level reset
instead of just the top of the Chisel-generated code.
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remove Tester.scala
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chisel-testers repo
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RegNext and RegInit should match Reg(next=) and Reg(init=)
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Option(null) returns None, but Some(null) returns Some(null)
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Move emit out of IR
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The return value of Bits.toBools doesn't need to be dynamically indexed
(as you could have just dynamically indexed the Bits itself), so
returning a Seq instead of a Vec is mroe appropriate.
This breaks a circular dependence between Bits and Vec, which helps
with macros/frontend refactoring.
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Include Chisel Frontend in JAR
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Seq to variatic argument list
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for source locator macros
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Closes #90
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Partially resolves #164
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@aswaterman closes #156
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Setting the io ref there wasn't doing anything meaningful
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The old blackbox behavior still emitted extmodules that have a
clk, reset pin and prepended all io's with io_ (ultimately). Most
verilog modules do not follow this distinction (or use a slightly
different name for clock and so on).
Thus, instead BlackBox has been rewritten to not assume a clk or
reset pin. Instead, the io Bundle specified is flattened directly
into the Module.ports declaration. The tests have been rewritten
to compensate for this. Also, added a test that uses the clock pin.
As a secondary change, the _clock and _reset module parameters were
bad for two reasons. One, they used null as a default, which is a
scala best practices violation. Two, they were just not good names.
Instead the primary constructor has been rewritten to take an
Option[Clock] called override_clock and an Option[Bool] called
override_reset, which default to None. (Note how the getOrElse call
down below is much more natural now.)
However, users may not want to specify the Some(their_clock) so I
also added secondary constructors that take parameters named clock
and reset and wrap them into Some calls into the primary constructor.
This is a better UX because now you can just stipulate clock=blah in
instantiation of that module in symmetry with using the clock in the
definition of the module by invoking clock.
PS: We could also back out of allowing any overrides via the Module
constructor and just require the instantiating Module to do
submodule.clock := newclock, etc.
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