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2019-08-06Avoid when(reset) construct in LFSRAndrew Waterman
Muxes and resets are only isomorphic with synchronous reset. Use a reset instead of a conditional to make this async-reset-safe.
2019-08-01Merge pull request #1139 from freechipsproject/deprecations-are-serious-businessSchuyler Eldridge
Remove Deprecations since before 3.2
2019-08-01Flatten *FactoryBase hierarchySchuyler Eldridge
This renames all *FactoryBase traits to *Factory, removes transparent *Factory objects, and propagates this flattened hierarchy throughout the codebase. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-01Remove anything deprecated since before 3.2Schuyler Eldridge
Anything removed by this that is used by the compatibility layer is migrated to the compatibility layer. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Fix deprecated Vec usage in chisel3.util.LFSR16Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Clarify Module deprecationsSchuyler Eldridge
This adds a clarification to the deprecation message for RawModule, MultiIOModule, UserModule, and ImplicitModule. While these were technically deprecated "since the beginning of time", this adds a comment that these aliases will be removed in 3.3. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Fix deprecation warningsSchuyler Eldridge
Change "since" specification from "chisel3.2" to "3.2". This aligns with usages in the rest of the codebase. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Merge pull request #1143 from ↵Schuyler Eldridge
freechipsproject/improve-compatibility-mode-testing Improve compatibility mode testing
2019-07-31Add SInt deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add UInt deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Bits deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add VecLike deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Wire deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Data deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add debug deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Mem/SeqMem deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add LFSR16 deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Queue deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Enum deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add BitPat deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Merge pull request #1142 from freechipsproject/enable-dummy-compatibility-testSchuyler Eldridge
Fixup and enable Dummy CompatibilitySpec test
2019-07-31Fixup and enable Dummy CompatibilitySpec testSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-01Fix shift register in READMEAdam Izraelevitz
2019-07-30Merge pull request #1138 from freechipsproject/core-deprecate-3.2Schuyler Eldridge
Core deprecation "since" should be "3.2" not "3.3"
2019-07-30Change core deprecation "since" from 3.3 -> 3.2Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-24Merge pull request #1129 from freechipsproject/num-maxwidthSchuyler Eldridge
Fix Num.+ Scaladoc
2019-07-24Fix Num.+ ScaladocSchuyler Eldridge
Change Num.+ Scaladoc to state that this is not a growing addition. Note that this is problematic either way as this macro is resolved to an abstract method. Classes implementing this typeclass are technically free to violate what we put in the Scaladoc here. h/t @kammoh Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-18Support Analog DontCare bulk-connect (#1056)Richard Lin
Short-term patch to enable this useful behavior. In the future, we may want to rearchitect the type system and/or rethink the more edge-case connect behavior.
2019-07-18Add width utility functions to avoid incorrect usage of bare log2Ceil(). (#819)Jim Lawson
* Add width utility functions to avoid incorrect usage of bare log2Ceil(). * Respond to comments: Remove apply(Data) method. Change name(s) to signedBitLength, unsignedBitLength. * Respond to comments - don't be lazy. Independently calculate the bit length to verify correct operation. * Respond to comments - return in.bitLength - 0 (not 1) for 0 * Respond to comments - update wdith for signed 0; add explicit tests. * Add comment expressing zero width wire assumption.
2019-07-16Fix typo in README.md (#1123)Henry Cook
2019-06-26Use Verilator 4.016 (#1116)Jim Lawson
* Use Verilator 4.016 Now that ucbbar/chisel3-tools has Verilator 4.016, use that for tests. * Update Verilator version in SETUP
2019-06-24Changed Value macro in ChiselEnum so that it doesn't use deprecated (#1104)Hasan Genc
function. This also fixes prior issue where ChiselEnums would not compile when @chiselName was applied to a module containing a ChiselEnum
2019-06-19First crack at updating the readme (#1106)Chick Markley
* First crack at updating the readme Goals Include up front example Simplify Get users to things quicker Move complicated details to wiki. * headers were not working, intellij and github don't use same render for .md files * Fix verb agreement * Add a fir filter diagram Compact the fir-filter code a bit * More compact filter * Additional README.md updates Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Don't use chisel-lang.org, drop HCL Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Fix link to fir image, make it relative * Proposed readme changes * Resize picture, restyle doc bullets
2019-06-11Added documentation to Decoupled, Conditionals, Counter (#1015)Adam Izraelevitz
* Added documentation to Decoupled, Conditionals, Counter * Fixed private Counter class error * Move Counter class deprecation and re-definition into util package object. * Revert "Move Counter class deprecation and re-definition into util package object." This reverts commit f61bdddf7051522363e1d203fcd46b512047c87d. * Restore the old Counter definition and address this in a separate PR. We can move the deprecation warning and the type definition into the util package object (see f61bdddf7051522363e1d203fcd46b512047c87d), but then we fail tests using Counter with a `ScalaReflectionException` in Aggregate.scala:779 (in def cloneType) when: `Some(mirror.reflect(this).symbol)` generates `type Counter is not a class`. * Made @ducky64 change to Counter doc Used to generate an inline (logic directly in the containing Module, no internal Module is created) hardware counter.
2019-06-03Merge pull request #1004 from freechipsproject/chisel-stageChick Markley
Chisel stage
2019-05-22Make Driver a ChiselStage compatibility layerSchuyler Eldridge
This converts the original chisel3.Driver to use chisel3.stage.ChiselStage. This is implemented in the following way: 1. ExecutionOptions are converted to an AnnotationSeq 2. The AnnotationSeq is preprocessed using phases contained in the Chisel DriverCompatibility objects. One of these *disables* the execution of FirrtlStage by ChiselStage. 3. ChiselStage runs on the preprocessed AnnotationSeq 4. The input ExecutionOptionsManager is mutated based on the output of ChiselStage. 5. The FIRRTL stage is re-enabled if it's supposed to run and selected FIRRTL DriverCompatibility phases run. 6. FirrtlStage runs 7. The output AnnotationSeq is "viewed" as a ChiselExecutionResult This modifies the original DriverSpec to make it more verbose with the addition of info statements. The functionality of the DriverSpec is unmodified. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add toAnnotations method to ChiselExecutionOptionsSchuyler Eldridge
Adds a method to enable conversion from ChiselExecutionOptions back to an AnnotationSeq. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add Driver Compatibility LayerSchuyler Eldridge
This includes phases necessary to provide backwards compatibility with the old Chisel3 Driver. These are placed in a DriverCompatibility object inside chisel3.stage.phases. The following four phases are included: - AddImplicitOutputFile (from a TopNameAnnotation) - AddImplicitOutputAnnotationFile phase - DisableFirrtlStage (to disable ChiselStage running FirrtlStage) - MutateOptionsManager (to update options after ChiselStage) - ReEnableFirrtlStage (to renable FirrtlStage if needed) Additionally, this adds a view of a ChiselExecutionResult for providing the legacy return type of the Chisel Driver. Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.ChiselStageSchuyler Eldridge
This adds ChiselStage, a reimplementation of chisel3.Driver as a firrtl.options.Stage. This is simplistically described as a pipeline of Phases. Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.MaybeFirrtlStageSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2019-05-22Add stage.phases.AddImplicitOutputAnnotationFileSchuyler Eldridge
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel.stage.phases.AddImplicitOutputFileSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.Emitter PhaseSchuyler Eldridge
This adds an Emitter Phase that writes a ChiselCircuitAnnotation to a file if a ChiselOutputFileAnnotation is present. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.Convert PhaseSchuyler Eldridge
This coalesces three distinct operations into one Convert Phase: 1. Chisel Circuit to FIRRTL Circuit (CHIRRTL) conversion 2. Conversion of Chisel Annotations to FIRRTL Annotations 3. Generation of RunFirrtlTransformAnnotations Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.Elaborate PhaseSchuyler Eldridge
This adds an Elaborate Phase that expands ChiselGeneratorAnnotations into ChiselCircuitAnnotations and deletes the original. Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.Checks PhaseSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add ChiselOptionsViewSchuyler Eldridge
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.ChiselOptionsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.ChiselCliSchuyler Eldridge
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage AnnotationsSchuyler Eldridge
This adds the following FIRRTL Annotations to Chisel: - NoRunFirrtlCompilerAnnotation - PrintFullStackTraceAnnotation - ChiselGeneratorAnnotation - ChiselCircuitAnnotation - ChiselOutputFileAnnotation This includes tests for ChiselGeneratorAnnotation as this Annotation is able to be constructed from a String and to elaborate itself. Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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