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2020-09-04Better Building of FIRRTL From Source (#1563)Jack Koenig
Using JVM system properties sbt.sourcemode and sbt.workspace, one can now easily build chisel3 with firrtl from source Example use: Assuming firrtl is cloned into the chisel3 root directory: $ sbt -Dsbt.sourcemode=true -Dsbt.workspace=$PWD Alternatively, one can set these properties in .sbtopts which can then be committed, enabling building from source by default
2020-09-03Bug fix for build.sc (#1579)Jiuyang Liu
2020-09-02Add chisel plugin to mill build system. (#1572)Jiuyang Liu
* add chisel plugin to mill build system. * update for review.
2020-08-27Restore and deprecate Chisel.Driver (#1571)Jack Koenig
It shouldn't be removed until we also remove the underlying chisel3.Driver.
2020-08-27Update README.md (#1570)Martin Schoeberl
A quick fix for the developer's confusion
2020-08-26Add ChiselPhase, Stop writing files in ChiselStage$ methods, Expand ↵Schuyler Eldridge
ChiselStage$ helpers (#1566) * Add ChiselPhase * Use ChiselPhase in ChiselStage, remove targets Switch from a one-off PhaseManager inside ChiselStage to actually using the newly added ChiselPhase. This removes the targets method (and API) from ChiselStage. * Stop writing to files in ChiselStage$ methods Change the ChiselStage companion object methods, elaborate and convert, to not write files. Under the hood, these are switched from using ChiselStage (which, like all phases, will write files) to using ChiselPhase. * Test that ChiselStage$ methods write no files Modify existing ChiselStage object method tests to check that no files are written. * Expand ChiselStage$ API with more helpers This adds additional methods to the ChiselStage object for going directly from a Chisel module to a string including: CHIRRTL, high FIRRTL IR, Verilog, and SystemVerilog. Differing from their ChiselStage class counterparts, these take no arguments other than the module and write no files. * Add tests of new ChiselStage$ helper methods * Use ChiselStage object in tests Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-08-25Relax plugin scalac phase order (#1568)Jack Koenig
It must run after the typer, but doesn't need to "run right after". The stricter dependency conflicted with the semanticdb-typer.
2020-08-21Updated PR template to include checklist and documentation updates (#1562)Adam Izraelevitz
* Updated PR template to include checklist and documentation updates * Change milestones to 3.x.x * updated milestones
2020-08-21Move multi-clock to explanations (#1561)Adam Izraelevitz
2020-08-21Added website docs and mdoc. (#1560)Adam Izraelevitz
* Added website docs and mdoc. Removed all warnings * Updated README and added build to circle ci * Added how to build documentation, deprecated wiki * Fix copypasta Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-08-20Remove use of PreservesAll, cleanup dependencies (#1558)Schuyler Eldridge
Remove usages of the deprecated trait PreservesAll and use an explicit false invalidates. Additionally, all phases are converted to be more canonical in there specification of dependencies by: 1. Overriding all default dependency implementations 2. Using def instead of val Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-08-14fix build release problem (#1556)Chick Markley
2020-08-13Move treadle dependency to the tests (#1554)Jack Koenig
Use inheritance to make TesterDriver Backend API extensible, then define a TreadleBackend in the test project
2020-08-13Bump Scala to 2.12.12 (#1553)Jack Koenig
Also fix BuildInfo in mill
2020-08-13Deprecate support for Scala 2.11 (#1551)Jack Koenig
Leverages chiselRuntimeDeprecated infrastructure. As such it is not currently suppressible.
2020-08-13Allow counters to be reset manually (#1527)Josh Bassett
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-08-12Deprecate Module.io and BlackBox.io (#1550)Jack Koenig
* Deprecate Module.io and BlackBox.io This is a step toward unification of Module with MultiIOModule. The future of BlackBox is a bit less clear, but its existing API can be maintained without the io virtual method. The trickier API to maintain is auto-IO wrapping for compatibility Modules and BlackBoxes. This will probably require reflection to support once the io virtual method is removed. * Improve deprecation warning for io
2020-08-12Switch to HowToSerialize for Emission (#1405)Schuyler Eldridge
* Fix emit{Firrtl,Verilog} for CustomFileEmission Change ChiselStage helper methods for emitting FIRRTL (emitFirrtl) and Verilog (emitVerilog) to look for Circuit and Verilog annotations instead of DeletedAnnotations. This is needed after migrating to the CustomFileEmission mixin in FIRRTL where FIRRTL will no longer delete emitter annotations. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Use CustomFileEmission for ChiselCircuitAnnotation Removes the explicit chisel3.phases.Emitter and instead does emission with a CustomFileEmission mixin to ChiselCircuitAnnotation. This then prevents the need for passing around DeletedAnnotations. As a consequence, I removed an unnecessary run of a second Converter in the Driver. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Fix tests for use of CustomFileEmission trait Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Fixes for newer CustomFileEmission API Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-08-11Bug fix for manipulating submodules in aspects (#1538)Justin Deters
* Fixed the aspect as parent bug in Data and MonoConnect * refactored and cleaned up finding an aspect parent * Added aspect fix to the BiConnect class * added unit test for manipulating submodules via aspects * Refactored to move determination of proper parent to Builder and made logic simpler in MonoConnect, Data, and BiConnect * Removed unused function and provided Scaladoc for retrieveParent
2020-08-11Restore Counter.n API (#1546)Jack Koenig
Includes special case support for Counter(0) which has identical behavior to Counter(1) except for the value of n.
2020-08-10Remove ChiselLegacyAnnotation (#1544)Jack Koenig
It was private and unused
2020-08-06Update OneHot.scala (#1539)Leigang Kou
comment fix only.
2020-07-31Check whether signals escape their when scopes (#1518)Albert Magyar
* Include and check when scoping as part of reg/mem/wire/node bindings * Allow outdated 'when' behavior of CHIRRTL memory ports with enables * Extend cross-module / when-visibility checks to all data refs * Fixes #1512 * Cannot be checked if outside a module context * E.g. delayed evaluation of printf / assert args * Add basic test cases for cross-module refs / signals escaping when scopes * Remove illegal cross-module references from existing tests
2020-07-31Add emitSystemVerilog method to ChiselStage (#1534)Tom Alcorn
2020-07-30Broken auto-clonetype on Scala 2.11.12 (#1480)Adam Izraelevitz
* Added broken auto-clonetype test * Added bugfix for 2.11 * Add descriptive comment for 2.11 special case * Update src/test/scala/chiselTests/AutoClonetypeSpec.scala * Update src/test/scala/chiselTests/AutoClonetypeSpec.scala Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-30Allow a counter to be instantiated using a Scala range (#1515)Josh Bassett
* Add positive range generator * Allow the Counter module to be instantiated with a Scala range * Use head/last to determine counter width Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> * Let counter overflow naturally when appropriate We only need to explicitly wrap counters that don't start at zero, or end on a power of two. Otherwise we just let the counter overflow naturally to avoid wasting an extra mux. * Require counter range to be non-empty Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-29Improved Chisel Naming via Compiler Plugins + Prefixing (#1448)Adam Izraelevitz
Added prefixing and a compiler plugin to improve naming. Only works for Scala 2.12 and above. Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-07-29Update build instructions in README (#1524)Josh Bassett
The instructions for building Chisel locally didn't include anything about firrtl or treadle. The steps are: 1. publishLocal current working copy of FIRRTL 2. publishLocal current working copy of Treadle 3. sbt test in chisel3
2020-07-28Select: update to work with records (#1525)Albert Chen
2020-07-25Using TreadleTesterPhase now requires new (#1520)Chick Markley
Treadle tester phase requires new to fix problems found when running tests in parallel.
2020-07-22Basic model checking API (#1499)Tom Alcorn
* Add `check(...)` affordance * Add assert (renamed from check and fixed) * Add verification statements * Move formal to experimental.verification * Make test use ChiselStage `generateFirrtl` has been cut from Chisel * Fix newly introduced style warnings * Fix some old style warnings for good measure * Revert "Fix some old style warnings for good measure" This reverts commit 31d51726c2faa4c277230104bd469ff7ffefc890. * Cut scalastyle comments * Cut formal delimiter comments
2020-07-21Merge pull request #1519 from freechipsproject/no-scalastyleAlbert Magyar
Remove scalastyle configurations
2020-07-21Remove scalastyle configs from repositoryAlbert Magyar
* Drop plugin * Drop scalastyle tests from make recipes * Remove checkstyle from CI
2020-07-21Delete outdated scalastyle configuration comments from sourceAlbert Magyar
2020-07-15Add Treadle to CI builds (#1516)Schuyler Eldridge
Change CI to build Treadle master from source. This fixes a bug where Treadle would be pulled from the latest snapshot (which would pull the latest FIRRTL snapshot). For bleeding edge PRs that rely on new FIRRTL features, using a FIRRTL snapshot may result in compilation failures. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-07-13Update Development Meetings info (#1511)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-13Provide an implementation of litOption() for BundleLits (#1280)Jim Lawson
2020-07-05fix treadle dependency for mill (#1504)Jiuyang Liu
* fix treadle dependency for mill * bug fix for test
2020-06-30Merge pull request #1483 from freechipsproject/add-treadle-backend-for-testsChick Markley
This adds a mechanism for the unittests to be run with the TreadleBac…
2020-06-29- A few final fixes after the rebasechick
2020-06-29This adds a mechanism for the unittests to be run with the TreadleBackendchick
This mechanism is not enabled and should not change the behavior of existing tests A following PR will deliver a switch that will allow changing the backend. The reasons for this PR - Treadle tests run much faster, enabling quicker debugging and CI cycles - This will help ensure fidelity of Treadle to the Verilator backend A few tests are marked as verilator only due to black box limitations Change treadle to a direct dependency I tried to make it a test only dependency but the TesterDriver sits in src/main requiring that regular compile have access to treadle Oops, made treadle the default A number of changes in response to @ducky64 review - made backend check clearer and add error handling for multiple backends specified - Fixed duplicate TargetDirAnnotation uses in Treadle backend - Cleaned up BlackBox test formatting - Undid unnecessary debugging changes from Counter - Undid .gitignore change, that should be on another PR A number of changes in response to @ducky64 review - Undid debugging changes made to BitWiseOps
2020-06-24Add missing finishWrapper call in TesterDriver (#1496)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-06-24Add .scala-steward.conf (#1495)Jim Lawson
2020-06-23Don't run FIRRTL in FlattenSpec's ChiselStage (#1493)Schuyler Eldridge
Fix a bug in FlattenSpec where ChiselStage was running the FIRRTL compiler in ChiselStage and then re-running the FIRRTL compiler. This changes it to be like InlineSpec and to not run FIRRTL during ChiselStage. This was manually backported to 3.3.x. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-22Merge pull request #1481 from freechipsproject/driver-deprecationsSchuyler Eldridge
Remove Deprecated Usages of chisel3.Driver, CircuitForm
2020-06-22Clarify chiselTests.Utils.extractCause ScaladocSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-22Code simplification in internal Chisel._ methodSchuyler Eldridge
Co-authored-by: Chick Markley <chick@qrhino.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-22Deprecate Driver Execution classesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-22Remove Driver usage from Chisel._ packageSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-22Remove Driver usage in EmitterSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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