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2021-01-20remove 2.11 dedicated code. (#1744)Jiuyang Liu
This PR revert #1480, but keep the test. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-01-20Fix Mergify condition for labeling backports (#1742)Jack Koenig
2021-01-19Add when.cond for getting the current when condition (#1694)Jack Koenig
This is useful for libraries to guard operations implemented via annotations or BlackBoxes by the current when predicate
2021-01-15Merge pull request #1732 from chipsalliance/farewell_scala_211Jack Koenig
Farewell Scala 2.11
2021-01-15farewell Scala 2.11Jiuyang liu
2021-01-11Make `toTarget` fail if called on a Literal (or would otherwise not ↵Megan Wachs
serialize properly) (#1714) * Add (failing) Test for Data toTarget calls Add scaladoc and clean up test * Builder: don't let .toTarget pass if it won't be able to deserialize properly later * Update src/test/scala/chiselTests/ReferenceTargetSpec.scala * Rename and simplify tests for literal toTarget
2021-01-06Update meeting url (#1716)Jiuyang Liu
2020-12-17Automate publishing of SNAPSHOTS with sbt-ci-release (#1706)Jack Koenig
2020-12-17Remove CircleCI (#1702)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-12-17Bump SNAPSHOT and SNAPSHOT dependencies (#1701)Jack Koenig
2020-12-16Switch to using Github Actions CI (#1690)Jack Koenig
MiMa binary compatibility checks are now run on master, but the mimaPreviousArtifacts are empty which makes the check a no-op. This helps keep both the build.sbt and CI more consistent between master and stable branches. .mergify.yml is also updated with mergify.sc from chisel-repo-tools using the following configuration: conditions: - status-success=all tests passed branches: - 3.2.x - 3.3.x - 3.4.x
2020-12-08Make Maven show chisel3 as apache-2.0 (#1695)Chick Markley
- fix build.sbt - fix build.sc
2020-12-07(encore) Builder: use LazyLogging.logger.warn to print elaboration message ↵Jiuyang Liu
(#1670) * Builder: use LazyLogging.logger.warn to print elaboration message * add deprecation for chisel3.internal.ErrorLog.info. * add test to check elaboration message still exist. Co-authored-by: Kevin Laeufer <kevin.laeufer@sifive.com>
2020-12-01Fix RegInit of Bundle lits (#1688)Jack Koenig
Implemented by folding Element.ref into Data.ref. Element.ref had special handling for literals, but because Bundles can also be literals, there were code paths that tried to get the ref of a Bundle literal which was non-existent. Now, all literals are handled together. Because FIRRTL does not have support for Bundle literals, Bundle literal refs are implemented by materializing a Wire.
2020-12-02readme: simplify sbt snippet and update to the latest stable release (#1686)Kevin Laeufer
2020-11-24Update some README links to chipsalliance (#1673)Jack Koenig
2020-11-16Improve source locators for switch statements. (#1669)Daniel Kasza
* Improve source locators for switch statements.
2020-11-11Add custom mdoc modifier for emitted Verilog (#1666)Jack Koenig
2020-11-11Ignore tests using System.setSecurityManager (#1661)Jack Koenig
The SecurityManager is global so is not thread-safe. This is the source of flaky tests in FIRRTL CI. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-11Refine autonaming to have more intuitive behavior (#1660)Jack Koenig
* Refine autonaming to have more intuitive behavior Last name in an Expression wins, while the first Statement to name wins. This is done via checking the _id of HasIds during autonaming and only applying a name if the HasId was created in the scope of autonaming. There is no change to .autoSeed or .suggestName behavior. Behavior of chisel3-plugins from before this change is maintained. * Update docs with naming plugin changes
2020-11-05For HasId.setRef, have first set win (with force override) (#1655)Jack Koenig
This is a refinement of the assertion added in #1616 then removed in #1654. Because Records now set the refs of children upon binding, later, unbound Records could incorrectly override the refs. The first set should win.
2020-11-03Remove Data.setRef assertion (#1654)Jack Koenig
It causes issues for some legal (if awkward) patterns. A larger refactor of when refs are set could reinstate this check.
2020-11-02SeqUtils asUInt endian-ness: hi/lo instead of right/left (#1647)John Ingalls
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-02Bugfix - adding external modules was broken (#1649)Adam Izraelevitz
2020-10-30Fix bug where refs may not get set for Records (#1645)Jack Koenig
This requires a combination of things, but it happens to be a combination used by Diplomacy in Rocket Chip. It must be a Record in compatibility code with Vecs as fields and a mix of components with and without set directions.
2020-10-27Fix broken links in docs (#1643)Adam Izraelevitz
2020-10-26Fix crosslinks in mdoc. Can't use md suffix (#1640)Adam Izraelevitz
* Fix crosslinks in mdoc. Can't use md suffix * Removed all .md crossrefs Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-10-26Bugfix - module name collision for injecting aspect (#1635)Adam Izraelevitz
* Bugfix - module name collision for injecting aspect * Fixed mechanism to avoid module name collisions * Added comments for reviewer feedback Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-10-26Added Force Name API (#1634)Adam Izraelevitz
* Added forcename transform and tests * Added documentation and additional error checking * Added mdoc. Added RunFirrtlTransform trait * Removed TODO comment * Addressed reviewer feedback * Removed trailing comma Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-10-26Fixed broken link to type hierarchy diagram (#1611)PENGUINLIONG
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-10-26Delete index.md (#1613)Adam Izraelevitz
Causes issues when building the website, using these docs. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-10-22Use Data refs for name prefixing with aggregate elements (#1616)Jack Koenig
* Use Data refs for name prefixing with aggregate elements Vecs set the refs of their elements upon construction of those elements. In the past, Records haven't set their elements refs until module close, but it can be done sooner. Doing it upon binding means that refs will at least be available for Records used in hardware elements. Since only bound Data can be connected to anyway, Aggregate elements being connected to will always have a ref which we can then use for creating naming prefixes. * Add tighter correctness checks * Handle more cases in connection prefixing Add support for forcing setRef to override a previous setting. This is only used by BlackBox ports which need to drop their io prefix. Also add a Try() around Data.bindingToString which sometimes throws exceptions when being used to .toString a Data in an error message. * Strip trailing spaces in names in compiler plugin
2020-10-21Make `-e` option work with ChiselStage methods (#1630)Schuyler Eldridge
* Fix `-e` option causing ChiselStage.emit* to error Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Add test of `-e` ChiselStage behavior Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * fixup! Add test of `-e` ChiselStage behavior
2020-10-19Change prefix stack to List[String] (#1617)Jack Koenig
This allows for sharing of the prefix stacks between Data, and removes a boxing per prefix stack element that is no longer necessary. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-10-19Enable Cat of Zero Element Vec (#1623)Schuyler Eldridge
* Return 0.U for asUInt of a zero-element Seq Add a condition to SeqUtils.asUInt to have it return an unspecified width 0.U when applied to an empty sequence. This enables the ability to do a Cat of a zero-element sequence. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Test elaboration of Cat on zero-element Seq Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2020-10-14Provide user source locators in Builder.error errors (#1618)Jack Koenig
Package chisel3 was not properly marked as an internal package so source locators in reported errors would point to files like Bits.scala.
2020-10-13ExtModule's lacked support built in support for providing (#1154)Chick Markley
* ExtModule's lacked support built in support for providing the verilog source. This changes creates traits that can be used with ExtModule to provide the support currently found in BlackBox - Add support for ExtModule helpers - HasExtModuleResource to use addResource - HasExtModuleInline to use setInline - HasExtModulePath to use addPath - Add tests of the above support. - Note: These tests use Stage instead of Driver - Added ScalaDoc for HasBlackBoxInline#setInline * Fix the danged trailing commas. * Change to use `.transform` as the correct API for `ChiselStage`
2020-10-12When prefixing with a data, eagly get local name (#1614)Jack Koenig
Fixes #1606 Previously, the Data itself would be put on the prefix stack and its full name would be used as the prefix for subsequent names. This meant that prefixes would grow quadratically as the prefix is present both on the Data pushed to the stack, and on the stack itself. This is fixed by just using the "local" name of the Data being pushed on the stack. A related issue is deferring the name resolution. This led to unintuitive behavior when the name of a Data used as a prefix is overridden later (usually when the Data is a return value). The overriding name would show up in prefixes twice instead of once. It is much more intuitive to grab the name at the moment of the connection creating the prefix rather than deferring to later. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-10-12Update junit to 4.13.1 (#1612)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-10-11Add 3.4.x to Mergify (#1607)Jack Koenig
2020-10-05Move more docs (#1601)Adam Izraelevitz
* Fix broken mdoc * Added test-chisel-docs to ci workflow * Add requirement on build-treadle job * Added forgotton colon * Forgot cd into chisel3 dir * moved three docs into explanations * Updated reference Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
Change source and other relevant files to use SPDX license LICENSE file moved from src/ to ./ Changed license file to refer to this per recommendation using_spdx_license_list_short_identifiers WARNING: Tests fail with as of yet undiagnosed error ``` [error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15 [error] Failed tests: [error] chiselTests.QueueSpec [error] examples.VendingMachineGeneratorSpec [error] chiselTests.HarnessSpec [error] chiselTests.ConnectSpec [error] chiselTests.aop.SelectSpec [error] chiselTests.PopCountSpec [error] chiselTests.CloneModuleSpec [error] (Test / test) sbt.TestsFailedException: Tests unsuccessful [error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM sbt:chisel3> ```
2020-09-24Fix broken mdoc (#1600)Adam Izraelevitz
* Fix broken mdoc * Added test-chisel-docs to ci workflow
2020-09-22Support using switch without importing SwitchContext (#1595)Jack Koenig
2020-09-15make parameters for util modules public (#1452)Albert Chen
Co-authored-by: Megan Wachs <megan@sifive.com>
2020-09-15Improve performance of ChiselPlugin (#1590)Jack Koenig
Use caching to reduce number of expensive lookups
2020-09-14Documentation and minor plugin changes. (#1573)Adam Izraelevitz
* Added documentation. Bugfix in plugin. Moved plugin APIs to separate package * Revert reg naming behavior (omit underscore) * Added documentation and a test * Addressed reviewer feedback.
2020-09-09Recursively generate one-hot multiplexers for aggregates (#1557)Jerry Zhao
Test all cases in ParameterizedOneHotTesters Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-09-09Add new annotation for Chisel Circuit serialization (#1580)Jack Koenig
ChiselCircuitAnnotation no longer extends CustomFileEmission, rather it is Unserializable. Also the --chisel-output-file is added to the ChiselCli. New phase AddSerializationAnnotations constructs a CircuitSerializationAnnotation from ChiselCircuitAnnotation and ChiselOutputFileAnnotation. Both .fir and .pb file formats are supported. Default format is .fir unless a --chisel-output-file is specified with a .pb extension.
2020-09-09Fix load memory from file to work with binary (#1583)HappyQuark
* fix loadMemoryFromFile to work with binary Passed in hexOrBinary parameter to ChiselLoadMemoryAnnotation * Added test for binary format support in loadMemoryFromFile * Added test for binary format support in loadMemoryFromFile
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