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AgeCommit message (Expand)Author
2021-04-19Update polymorphism-and-parameterization.md (#1868)Fabien Marteau
2021-04-15update CCC2021 info (#1861)Jiuyang Liu
2021-04-15Improve Mergify labeling of backports (#1865)Jack Koenig
2021-04-14Fix doc formatting and generation (#1863)Carlos Eduardo
2021-04-12Add "how to tie off to 0" to the Cookbook (#1857)Megan Wachs
2021-04-07Update PULL_REQUEST_TEMPLATE.md (#1856)Megan Wachs
2021-04-07Add documentation guide about memory initialization (#1850)Carlos Eduardo
2021-04-01Fix Gitter chat room link (#1848)XinJun Ma
2021-03-31Fix formatting issue of links (#1844)Kalamár Ödön
2021-03-29Provide useful message on Vec.apply require (#1838)Jack Koenig
2021-03-27CCC 2021 placeholder (#1794)Jiuyang Liu
2021-03-23Make plugin autoclonetype always on (#1826)Jack Koenig
2021-03-18Update the FAQ and add doc on versioning (#1827)Jack Koenig
2021-03-18Reorganize website docs (#1806)Megan Wachs
2021-03-18Add toString method to BitPat (#1819)Boyang Han
2021-03-18Don't toggle top.cpp clock and reset on same cycle (#1820)Schuyler Eldridge
2021-03-17Fix incorrect usage of emitFirrtl in test (#1817)Schuyler Eldridge
2021-03-15allowReflectiveAutoCloneType must work outside of Builder context (#1811)Jack Koenig
2021-03-12Merge pull request #1804 from chipsalliance/autoclonetype2Jack Koenig
2021-03-12[plugin] Disable BundleComponent by default, add option to enableJack Koenig
2021-03-12[plugin] Stop autoclonetype stack traces when using pluginJack Koenig
2021-03-12[plugin] Implement autoclonetype in the compiler pluginJack Koenig
2021-03-11[plugin] Split ChiselComponent into its own fileJack Koenig
2021-03-11Import memory files inline for Verilog generation (#1805)Carlos Eduardo
2021-03-03Add header for chisel-enum.md (#1800)Jack Koenig
2021-03-02Adding ChiselEnum Documentation Entry (#1795)chrisbaldwin2
2021-03-01Fix conversions between DecoupledIO and IrrevocableIO (#1781)Jerry Zhao
2021-02-26Expose AnnotationSeq to Module. (#1731)Jiuyang Liu
2021-02-24Aggregate: fix typo (#1789)edwardcwang
2021-02-11Fix stack trace trimming across Driver/ChiselStage (#1771)Schuyler Eldridge
2021-02-10Merge pull request #1624 from chipsalliance/gc-dataJack Koenig
2021-02-09Make it possible to GC Data instancesJack Koenig
2021-02-09Add no-plugin-tests for testing Chisel without the compiler pluginJack Koenig
2021-02-08Parametrized Mem- & SyncReadMem-based implementation of the Queue class (#1740)Vladimir Milovanović
2021-02-05Add file line to source link from scaladoc (#1776)John's Brew
2021-02-04Minor docs improvements (#1774)Jack Koenig
2021-02-03Remove Deprecated APIs (#1730)Jiuyang Liu
2021-02-01Update reported width from div/rem to match FIRRTL results (#1748)Albert Magyar
2021-02-01Bump to Scala 2.12.13 (#1766)Jack Koenig
2021-01-27Fix some typo and using foreach instead of map in BoringUtils (#1755)SoyaOhnishi
2021-01-27Fix incorrect comment in ScalaDoc (#1756)Jack Koenig
2021-01-24Refactor EnumAnnotations and EnumFactory (#1747)SoyaOhnishi
2021-01-22Add redirect for Scala 2.11 upgrade page (#1749)Jack Koenig
2021-01-21Merge pull request #1745 from chipsalliance/remove-val-ioJack Koenig
2021-01-21Apply suggestions from code reviewJack Koenig
2021-01-21Update docs for the removal of val io and MultiIOModuleJack Koenig
2021-01-21Fold Chisel.CompatibilityModule into chisel3.internal.LegacyModuleJack Koenig
2021-01-21Remove val ioJack Koenig
2021-01-21Deprecate override_clock and override_reset in ModuleJack Koenig
2021-01-21Rename MultiIOModule to ModuleJack Koenig
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