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2021-06-16implement abstract Minimizer as a general API.Jiuyang Liu
2021-06-16fix for 2.13Jiuyang Liu
2021-06-16TruthTable can merge same inputs now.Jiuyang Liu
2021-06-16implement DecodeTableAnnotation for decode table caching.Jiuyang Liu
2021-06-16implement TruthTable to represent a decode table.Jiuyang Liu
2021-06-14explain sub-projects in README (#1962)Deborah Soung
* explain sub-projects * Update README.md Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Megan Wachs <megan@sifive.com>
2021-06-10Stop Emitting BlackBoxResourceAnno (#1954)Schuyler Eldridge
* Change HasBlackBoxResource to Resolve Resources Change HasBlackBoxResource to resolve resources immediately and emit BlackBoxInlineAnno instead of a BlackBoxResourceAnno. This removes the need for a FIRRTL compiler to grok the Java Resource API in order to handle BlackBoxResourceAnno. Emit BlackBoxInlineAnno from HasExtModuleResource instead of BlackBoxResourceAnno. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-06-04Update sbt-scalafix to 0.9.29 (#1948)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-06-04Update os-lib to 0.7.8 (#1949)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-06-04Update sbt-scoverage to 1.8.2Scala Steward
2021-06-02CCC schedule update (#1947)Jiuyang Liu
2021-05-28remove testOnly, since upstream implemented it. (#1946)Jiuyang Liu
2021-05-27Update sbt-mima-plugin to 0.9.2Scala Steward
2021-05-25throw exception if BitPat width is 0 (#1920)Jiuyang Liu
* spot a bug when BitPat width is 0 * fix #1919 Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-25make mill support 2.13. (#1934)Jiuyang Liu
2021-05-21Update sbt-scoverage to 1.8.1 (#1924)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-21Update sbt-scalafix to 0.9.28 (#1931)Scala Steward
2021-05-20doc: link to developer style guide (#1929)Martin Schoeberl
2021-05-20Implement PLA (#1912)Jiuyang Liu
* implement pla * implement test for pla * implement inverter matrix of PLA generator * fix for review. Co-authored-by: Boyang Han <yqszxx@gmail.com>
2021-05-20implement model checking API for chiseltest (#1910)Jiuyang Liu
* add os-lib to dependency. * implement EndToEndSMTBaseSpec * rename to SMTModelCheckingSpec * add documentation. * fix for review.
2021-05-17remove scopt dependency. (#1917)Jiuyang Liu
2021-05-17Update scala-compiler, scala-library, ... to 2.13.6Scala Steward
2021-05-17Update sbt-mima-plugin to 0.9.1 (#1915)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-15Update sbt-mdoc to 2.2.21 (#1916)Scala Steward
2021-05-12Update scalacheck-1-14 to 3.2.2.0 (#1908)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-12Update sbt to 1.5.2 (#1907)Scala Steward
2021-05-11Update sbt to 1.3.13 (#1501)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-11Update scalacheck-1-14, ... to 3.1.4.0 (#1575)Scala Steward
* Update scalacheck-1-14, ... to 3.1.4.0 * Update scalacheck-1-14, ... to 3.1.4.0 * Update scalacheck-1-14 to 3.1.4.0 Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-11Update sbt-scoverage to 1.8.0 (#1905)Scala Steward
2021-05-10implement equal to BitPat. (#1867)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-09Fix ShiftRegister with 0 delay. (#1903)Jiuyang Liu
* Add test to check ShiftRegister(s) with delay is 0. This should break ShiftRegister(x, 0) since last is not exist in a empty Seq. Originally, test only test 1 to 4, which missed a potential bug from #1723. * Fix ShiftRegister with 0 delay. if ShiftRegisters is empty, java will complain: ``` java.util.NoSuchElementException scala.collection.LinearSeqOptimized.last(LinearSeqOptimized.scala:150) ``` This fix this issue and return `in` directly when ShiftRegister size is 0. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-07Update sbt-mima-plugin to 0.9.0 (#1900)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2021-05-06add ShiftRegisters to expose register inside ShiftRegister. (#1723)Jiuyang Liu
* add ShiftRegisters to expose register inside ShiftRegister. * use Seq.iter for oneline implementation.
2021-05-05Remove chisel3.stage.phases.DriverCompatibility (#1772)Schuyler Eldridge
2021-05-04Update sbt-scoverage to 1.7.3 (#1899)Scala Steward
2021-04-30add helper function to convert chirrtl to firrtl. (#1854)Jiuyang Liu
* add convert(chirrtl: cir.Circuit): fir.Circuit to convert chirrtl to firrtl. * add scaladoc. * add test. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-29Scala 2.13 support (#1751)Jack Koenig
2021-04-29verification: guard statements with module reset (#1891)Kevin Laeufer
2021-04-29Update sbt-ci-release to 1.5.7 (#1832)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-29Update sbt-mdoc to 2.2.20 (#1870)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-29Update sbt-scalafix to 0.9.27 (#1842)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-29Update scopt to 4.0.1 (#1815)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-29Update sbt-scoverage to 1.7.0 (#1887)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-28Cookbook: clean up desiredName example (#1886)Megan Wachs
* Cookbook: clean up desiredName example * Update cookbook.md
2021-04-27Introduce VecLiterals (#1834)Chick Markley
This PR provides for support for Vec literals. They can be one of two forms Inferred: ``` Vec.Lit(0x1.U, 0x2.U) ``` or explicit: ``` Vec(2, UInt(4.W)).Lit(0 -> 0x1.U, 1 -> 0x2.U) ``` - Explicit form allows for partial, or sparse, literals. - Vec literals can be used as Register initializers - Arbitrary nesting (consistent with type constraints is allowed)
2021-04-26Cookbooks: make examples more clear and remove naming (#1881)Megan Wachs
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-26Add some error context to Converter .getRefs (#1878)Jack Koenig
2021-04-26Fix Gitter link in README (#1879)Jack Koenig
2021-04-21fixing context bug (#1874)Deborah Soung
2021-04-21Add a link to the Chisel book (#1872)Martin Schoeberl
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