summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2021-07-13fix for GitHub Action missing ivy FIRRTL.Jiuyang Liu
2021-07-13refactor github actionJiuyang Liu
2021-07-12Update sbt to 1.5.5Scala Steward
2021-07-09Fix chisel3 <> for Bundles that contain compatibility Bundles (Take 2) (#2031)Jack Koenig
PR #2023 fixed a composition issue for chisel3 biconnects delegating to FIRRTL partial connect when compatibility mode Bundles are elements of chisel3 Bundles. It missed an important case though that caused previously working code to break. The bug is fixed by doing the automatic flipping for compatibility mode Bundles that have "Input" as a direction in addition to those that are "Flipped".
2021-07-08Make it legal for concrete resets to drive abstract reset (#2018)Jack Koenig
This has been legal in FIRRTL since v1.2.3 (when reset inference started using a unification-style algorithm) but was never exposed in the Chisel API. Also delete the overridden connects in AsyncReset and ResetType which just duplicate logic from MonoConnect.
2021-07-08Fix chisel3 <> for Bundles that contain compatibility Bundles (#2023)Jack Koenig
BiConnect in chisel3 delegates to FIRRTL <- semantics whenever it hits a Bundle defined in `import Chisel._`. Because chisel3 <> is commutative it needs to be mindful of flippedness when emitting a FIRRTL <- (which is *not* commutative).
2021-07-08Add `isOneOf` method to `ChiselEnum` (#1966)Verneri Hirvonen
* Add @ekiwi's code as a starting point * Add test for ChiselEnum isOneOf method * Make isOneOfTester naming consistent with other testers * Add scaladoc comments for isOneOf * Add isOneOf tests that use the method that takes variable number of args * Add guide level documentation example for isOneOf
2021-07-08Update docs on dontTouch as optimization barrier (#2015)Schuyler Eldridge
Change the Scaladoc for the dontTouch utility. Indicate that this is an _optimization barrier_ and not just a guarantee that the signal won't be removed. The optimization barrier interpretation is the current implementation in the Scala FIRRTL Compiler. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-07-07Fix ChiselEnum docs (#2016)Jack Koenig
Also add newline to end of `verilog` modifier code blocks so that there is always a newline between code blocks and following material.
2021-07-06Make printf return BaseSim subclass so it can be named/annotated (#1992)Deborah Soung
2021-07-01Merge pull request #1999 from chipsalliance/fix-chiselenum-warningsJack Koenig
Fix ChiselEnum warnings and use Logger for warnings instead of println
2021-07-01Update docs for ChiselEnumJack Koenig
2021-07-01Add ChiselEnum.safe factory method and avoid warningJack Koenig
Previously, ChiselEnum would warn any time a UInt is converted to an Enum. There was no way to suppress this warning. Now there is a factory method (`.safe`) that does not warn and returns (Enum, Bool) where the Bool is the result of calling .isValid on an Enum object. The regular UInt cast is also now smarter and will not warn if all bitvectors of the width of the Enum are legal states.
2021-07-01Change Chisel warnings to use logger instead of printlnJack Koenig
It also uses the same logger as the Builder so that if we ever refactor that to be passed as an argument, it will be the same logger for both Builder and warning reporting.
2021-06-30Add 7 segment display decoder test caseBoyang Han
2021-06-29Merge pull request #1993 from chipsalliance/fix-select-clonemoduleasrecordJack Koenig
Fix aop.Select behavior for CloneModuleAsRecord
2021-06-29Change behavior of aop.Select to not include CloneModuleAsRecordJack Koenig
Previously, CloneModuleAsRecord clones would result in the same BaseModule object coming up multiple times when using APIs like .instances, .collectDeep, and .getDeep. This was not the intended behavior and can lead to very subtle bugs.
2021-06-29Restore aop.Select behavior for CloneModuleAsRecordJack Koenig
2021-06-29updated readme to mention verilator dependency (#1984)anniej-sifive
* added to readme * Update README.md Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-06-29deprecate getPorts with modulePorts. (#1945)Jiuyang Liu
* deprecate getPorts with modulePorts. * add doc to fullModulePorts and update deprecation notes. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-06-28Merge pull request #1974 from chipsalliance/fix-clonemoduleasrecord-totargetJack Koenig
Fix CloneModuleAsRecord support for .toTarget
2021-06-28Set refs for ModuleClone and ClonePorts in less hacky wayJack Koenig
2021-06-28Fix CloneModuleAsRecord support for .toTargetJack Koenig
2021-06-28CCC update (#1982)Jiuyang Liu
2021-06-28Add link to Chisel Breakdown slides to README (#1979)Jack Koenig
2021-06-25Update type_hierarchy (#1977)Jack Koenig
* Add Clock * Add Analog * Add Interval * Add line from User Types (...) to Record
2021-06-25Correct typos in core/src/main/scala/chisel3/Num.scala (#1976)Felix Yan
2021-06-24create and extend annotatable BaseSim class for verification nodes (#1968)Deborah Soung
* prototype annotating verif constructs * switch to final class * name emissions * moving BaseSim to experimental * adding name tests * fixing quotation escapes * emitting names, but everything has a default name * only name things with provided/suggested names * name every BaseSim node * removing msg, unused imports * fixing file exist calls
2021-06-23CCC info update (#1969)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-06-23Replace hard coded line separators with system specific onesBoyang Han
2021-06-21Bump scalatest to 3.2.9 (#1965)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-06-21Switch to Github Actions CI Badge (#1967)Jack Koenig
2021-06-16getVerilog in Chisel3 (#1921)Martin Schoeberl
2021-06-16Update sbt-buildinfo to 0.10.0 (#1545)Scala Steward
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-06-16Update sbt to 1.5.4 (#1960)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-06-16implement test for qmcJiuyang Liu
2021-06-16Add computational complexity analysisBoyang Han
2021-06-16Refactor to a more `scala` formBoyang Han
2021-06-16Merge minimized table before return as a TruthTableBoyang Han
2021-06-16implement QMC.Boyang Han
2021-06-16Apply Jack's Review Jiuyang Liu
1. `TruthTable` is final now. 2. add return type for `TruthTable` Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-06-16add documentation for DecodeTableAnnotation.Jiuyang Liu
2021-06-16Add test cases.Jiuyang Liu
2021-06-16switch to EndToEndSMTBaseSpecJiuyang Liu
2021-06-16Add minimized form of test casesBoyang Han
2021-06-16use z3 formal check minimized circuit and reference model.Jiuyang Liu
2021-06-16test decode cache.Jiuyang Liu
2021-06-16remove all timeouts by review.Jiuyang Liu
2021-06-16async decoder with 5 seconds timeout.Jiuyang Liu
2021-06-16add a simple decoder API.Jiuyang Liu
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-10 05:44:39 +0000