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2021-09-13Update scala-compiler, scala-library, ... to 2.12.14 (#1950)Scala Steward
2021-09-13Update sbt-mima-plugin to 1.0.0 (#2086)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-09-08Restore return type of BaseModule.toTarget to ModuleTarget (#2117)Jack Koenig
Definition/Instance introduced the need for representing the targets of instances as InstanceTargets. This original implementation changed the return type of BaseModule.toTarget to express this need. This is a backwards incompatible change that is actually unnecessary because it is impossible for users to get references to the internal InstanceClone objects, instead only accessing such modules via Instance[_] wrappers and cloned Data. We restored the old API by adding a new internal method "getTarget" which will give the correct targets for InstanceClones while maintaining the API of BaseModule.toTarget.
2021-09-08Update sbt installation instructions (#2115)Martin Schoeberl
* Update sbt installation instructions The bintray reference is dead. * fix grammar
2021-09-07Merge pull request #2113 from yqszxx/fix-pla-dcto1Jiuyang Liu
Fix a bug causes incorrect pla generation when input is `?`
2021-09-06Fix #2112, handle `?->1` caseBoyang Han
2021-09-06Test case reworkBoyang Han
2021-09-06Add a test case to demonstrate the bug found in #2112Boyang Han
2021-09-05Update sbt-mdoc to 2.2.23 (#2091)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-09-05Add Definition and Instance API (#2045)Adam Izraelevitz
This introduces a new experimental API for module instantiation that disentagles elaborating the definition (or implementation) from instantiation of a given module. This solves Chisel's longstanding reliance on "Deduplication" for generating Verilog with multiple instances of the same module. The new API resides in package chisel3.experimental.hierarchy. Please see the hierarchy ScalaDoc, documentation, and tests for examples of use. Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-08-31Fix chisel3 <> for compatibility Bundles (Take 3) (#2093)Jack Koenig
Previous incomplete fixes in #2023 and #2031. The legality of a FIRRTL connection is determined by type and flow. Chisel does not have access to true flow information. Previous fix attempts tried to use ActualDirection as a stand-in for flow, but it is incorrect in many cases. This new approach checks the flows of the lvalue and rvalues in the connect and flips the connection if either the lvalue cannot be a sink or the rvalue cannot be a source.
2021-08-30SyncReadMem: fix bug with read(addr) and add some formal tests (#2092)Kevin Laeufer
2021-08-30FIx firrtl typo in README versioning section (#2097)Megan Wachs
2021-08-26add new APIs to BitPat (#2076)Jiuyang Liu
* add Y and N to BitPat. * add ## for BitPat. * add rawString API. * use rawString in decoder * add select and slice to BitPat.
2021-08-25replace custom model checker with chiseltest formal verify command (#2075)Kevin Laeufer
* replace custom model checker with chiseltest formal verify command * integration-tests can make use of chiseltest This is a compromise solution to avoid issues with binary compatibility breaking changes in chisel3. * ci: move integration tests into separate job * run integration tests only for one scala version * ci: install espresso for integration tests * Update build.sbt Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
2021-08-24Add backport policy to PR Template (#2085)Jack Koenig
2021-08-23Merge pull request #2083 from chipsalliance/lazy-fir-emissionJack Koenig
Lazy .fir Emission
2021-08-23Use BufferedCustomFileEmission in CircuitSerializationAnnotationJack Koenig
2021-08-23Emit .fir lazily, overcomes JVM 2 GiB String limitJack Koenig
2021-08-23Remove chisel3's own firrtl Emitter, use firrtl SerializerJack Koenig
This will be slightly slower as it involves converting from Chisel modules to FIRRTL modules before turning them into Strings. This cost is somewhat mitigated by doing that conversion lazily such that we never materialize the entire firrtl Circuit in memory, only 1 module at a time.
2021-08-23Add multiple dimensions to VecInit fill and iterate (#2065)anniej-sifive
Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-08-21Update ChiselStage.scala (#2082)Ruige Lee
There might be some "@"?
2021-08-18Builder: downgrade "Elaborating design" message to info (#2081)Kevin Laeufer
2021-08-18Merge pull request #2057 from chipsalliance/fix_z3_ciJiuyang Liu
Z3 CI debug
2021-08-18switch espresso to ninja.Jiuyang Liu
2021-08-18timestamp seems to be fixed in actions/cache#397Jiuyang Liu
2021-08-18don't hit cacheJiuyang Liu
2021-08-18apt install ninjaJiuyang Liu
2021-08-18switch to ninjaJiuyang Liu
2021-08-18Revert "Just install z3 from apt-get in CI (#2056)"Jiuyang Liu
This reverts commit 1e7829eb674eed85a4cd537896d9fd9ee0bc5ff4.
2021-08-18Revert "remove DefRegInit, change DefReg API with option definition. ↵Jack Koenig
(#1944)" (#2080) This reverts commit ed894c61474c8bc73761a6c360ef9d14505d853b.
2021-08-17[docs] Add example of stripping directions from type (#2074)Jack Koenig
* [docs] Add example of stripping directions from type * Apply suggestions from code review Co-authored-by: Megan Wachs <megan@sifive.com> * Improve := comment Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-08-17remove DefRegInit, change DefReg API with option definition. (#1944)Jiuyang Liu
* remove DefRegInit, change DefReg API with option defination. * add error message * use Option[RegInitIR]. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-08-17Merge pull request #2072 from scala-steward/update/sbt-scalafix-0.9.30Jiuyang Liu
Update sbt-scalafix to 0.9.30
2021-08-16Update sbt-scalafix to 0.9.30Scala Steward
2021-08-12Add DataView (#1955)Jack Koenig
DataView is a mechanism for "viewing" Scala objects as a subtype of `Data`. Often, this is useful for viewing one subtype of `Data`, as another. One can think about a DataView as a cross between a customizable cast and an untagged union. A DataView has a Target type `T`, and a View type `V`. DataView requires that an implementation of `DataProduct` is available for Target types. DataProduct is a type class that provides a way to iterate on `Data` children of objects of implementing types. If a DataView is provided for a type T to a type V, then the function .viewAs[V] (of type T => V) is available. The object (of type T) returned by .viewAs is called a "View" and can be used as both an rvalue and an lvalue. Unlike when using an .asTypeOf cast, connecting to a "View" will connect to the associated field or fields of the underlying Target. DataView also enables .viewAsSupertype which is available for viewing Bundles as a parent Bundle type. It is similar to .viewAs but requires a prototype object of the Target type which will be cloned in order to create the returned View. .viewAsSupertype maps between the corresponding fields of the parent and child Bundle types.
2021-08-12Merge pull request #2066 from yqszxx/espresso-stdioJiuyang Liu
Pass truth table to espresso using stdin instead of temp file
2021-08-12Pass truth table to espresso using stdin instead of temp fileBoyang Han
2021-08-05Small changes to memory doc (#2062)Chick Markley
* Small changes to memory doc - Fixed typo "except" => "accept" - Use `Counter` explicitly in ROM section example. * Fix counter doc compile error * remove invisible doc block in memory example * more small fixes to make mem example pass doc compile * Get rid of sine wave iterator in memory doc * get rid of tabs on VecInit example * get rid of tabs on VecInit example
2021-08-04Added VecInit factory methods (fill,iterate) (#2059)anniej-sifive
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-08-03Added flush capability to Queue (#2030)anniej-sifive
Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Deborah Soung <debs@sifive.com>
2021-07-28Just install z3 from apt-get in CI (#2056)Jack Koenig
2021-07-28Bundles can no longer be instantiated with bound hardware (#2046)Jared Barocsi
Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-07-27Clarify test dependencies in README, add noplugin (#2053)Megan Wachs
There are now more tool dependecies than just `verilator` to get the full test suite to pass. Also add instructions for running the tests without the compiler plugin,
2021-07-23Update sbt-mdoc to 2.2.22 (#2047)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-07-22MovingAverage3 => MovingSum3 (#2050)Jack Koenig
The example in the README is a sum, not an average.
2021-07-14Fix Cat rename signal (#2011)Leway Colin
Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-07-14Espresso Decoder (#1964)Jiuyang Liu
Co-authored-by: Haoran Yuan <sinofp@tuta.io> Co-authored-by: Boyang Han <yqszxx@gmail.com>
2021-07-13Merge pull request #2041 from chipsalliance/ci_testJiuyang Liu
Fix CI.
2021-07-13fix ci, add more matrix.Jiuyang Liu