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2022-03-09Support BlackBoxes in D/I (#2438) (#2442)mergify[bot]
Also delete an errant println in InstanceSpec (cherry picked from commit 3462c54c018a52a377f1c89121b6ed99c5b0ae1d) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-03-08Add scanLeftOr and scanRightOr utilies (#2407) (#2437)mergify[bot]
Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 73d3c26029c07c17ce179dfead092eab4fb8ae2c) Co-authored-by: Liu Xiaoyi <circuitcoder0@gmail.com>
2022-03-07Tweaks to the Verilog-vs-Chisel Page (#2432) (#2433)mergify[bot]
* Tweaks to the Verilog-vs-Chisel Page * Update cookbook.md * Update verilog-vs-chisel.md * Update verilog-vs-chisel.md (cherry picked from commit 7432bdff8369ba55db73c7934e41bb6f4060bb6d) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-03-04Add SVG Version of Bundle Example Diagram (#2425) (#2431)mergify[bot]
(cherry picked from commit 98fdfc5e609099cb4fb1749132cc62236148c6da) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-03-04Issue errors on out-of-range extracts when width is known (#2428) (#2429)mergify[bot]
* Issue errors on out-of-range extracts when width is known Firrtl will catch this later on, but better to error early if possible. * Test that errors are generated on OOB extracts when width is known (cherry picked from commit 462def429aa87becb544533880a3075a806c53e4) Co-authored-by: Andrew Waterman <andrew@sifive.com>
2022-03-03Add Verilog-chisel side by side Reference Page to Docs (#2323) (#2426)mergify[bot]
Co-authored-by: Shola Ogunkelu @Shorla Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Deborah Soung <debs@sifive.com> Completed as part of Outreachy Internship Dec 2021-March 2022. (cherry picked from commit 362702f3fd79bf1071db4acecc679f25a0b94a8a) Co-authored-by: Olushola Ogunkelu <77856859+Shorla@users.noreply.github.com>
2022-02-15Make TruthTable accept unknown input width (#2387) (#2417)mergify[bot]
Widths are now padded to the maximum width of the inputs. Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 546b4e13fe90ff09d24b63664c072d46c13c0c38) Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2022-02-11Hierarchy API: make Mems lookupable (#2404) (#2410)mergify[bot]
(cherry picked from commit 2a985ac376698a2e6300fbee13001d82d3e13989) Co-authored-by: Deborah Soung <debs@sifive.com>
2022-02-10Make Tuple2 Lookupable (#2372) (#2406)mergify[bot]
(cherry picked from commit 024847d75079a125e5946e9dcf2ed9c14d2db730) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-02-08Overload getVerilogString to accept arguments (#2401) (#2402)mergify[bot]
(cherry picked from commit b55dc36d4edd1d22db37616235c003c89d68d29b) Co-authored-by: Carlos Eduardo <me@carlosedp.com>
2022-02-08Merge branch '3.5.x' into 3.5-releaseJack
2022-02-08Bump version strings.Jack
2022-02-04Fix variable-name typo (#2397) (#2400)mergify[bot]
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 015755749caa8a05f3809d446b023df80c7419d1) Co-authored-by: Tynan McAuley <tynan@galois.com>
2022-02-04Fix bundle elements performance regression (#2396) (#2398)mergify[bot]
* Only call _elementsImpl once in Bundle.elements * Distinguish compiler plugin and reflective _elementsImpl Bundle.elements now will only do post-processing if the user is using plugin-generated _elementsImpl. This improves performance for the case where the user does not opt-in to using the plugin to generate _elementsImpl. (cherry picked from commit 5fead89ee0132355e551bcb6b87cc2a6db679bee) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-02-03FillInterleaved documentation: swap order of elements in Seq example (#2393) ↵mergify[bot]
(#2395) (cherry picked from commit 055a85298c46c6734880cd828af436adbded1d0a) Co-authored-by: John Ingalls <43973001+ingallsj@users.noreply.github.com>
2022-02-03Tweak Bundle._elementsImpl (#2390) (#2392)mergify[bot]
* Change type of Bundle._elementsImpl to Iterable It was previously SeqMap (ListMap on Scala 2.12). This change gives us more freedom to optimize the implementation without breaking binary compatibility. It is scala.collection.Iterable because it is perfectly fine to return mutable collections (like Arrays) since the only use is to Iterate on them. * Disallow users implementing Bundle._elementsImpl Currently, it would result in a runtime linkage error. This turns it into a compile-time error. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 1b05a14ad6d5784f3b91ab510dc1095423c23ea8) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-02-03Tweak new mem port clock warnings (#2389) (#2391)mergify[bot]
Use Builder.deprecated instead of Builder.warning so that the warnings are aggregated by source locator to prevent spamming the screen with duplicated warnings. (cherry picked from commit 538e223ae81c8b66a4123303f6dab61c874aaa1e) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-02-02Add Scala 2.13.8 to plugin cross-compilation (#2385) (#2386)mergify[bot]
(cherry picked from commit 551854b223954f359156582c4219948dbb328857) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-02-01Improve error reporting (backport #2376) (#2379)mergify[bot]
* Improve error reporting (#2376) * Do not trim stack traces of exceptions with no stack trace This prevents us from accidentally giving stack traces to exceptions that don't have them and giving misleading messages telling users to use --full-stacktrace when it won't actually do anything. Also deprecate ChiselException.chiselStackTrace which is no longer being used anywhere in this codebase. * Add exception class for multiple-errors reported New chisel3.internal.Errors replaces old anonymous class that would show up as chisel3.internal.ErrorLog$$anon$1 in error messages. * Add new option --throw-on-first-error This tells Chisel not to aggregate recoverable errors but instead to throw an exception on the first one. This gives a stack trace for users who need it for debugging. (cherry picked from commit ff2e9c92247b3848659fa09fdd53ddde2120036a) * Waive MiMa false positives The waived change is to a package private constructor. Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2022-02-01Optional clock param for memory ports (#2333) (#2382)mergify[bot]
Warn if clock at memory instantiation differs from clock bound at port creation and port clock is not manually passed Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 465805ec7b2696a985eaa12cf9c6868f11ac2931) Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
2022-02-01Chisel plugin bundle elements handler (#2306) (#2380)mergify[bot]
Adds generation of `Bundle.elements` method to the chores done by the compiler plugin For each `Bundle` find the relevant visible Chisel field members and construct a hard-coded list of the elements and their names implemented as `_elementsImpl` For more details: See plugins/README.md - Should be no change in API - Handles inheritance and mixins - Handles Seq[Data] - Tests in BundleElementSpec Co-authored-by: chick <chick.markley@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 237200a420581519f29149cbae9b3e968c0d01fc) Co-authored-by: Chick Markley <chick@qrhino.com>
2022-01-28Fix Decoder bug for constant 0 and DC (#2363) (#2371)mergify[bot]
* Fix the QMC bug for constant and dontcare output. * Fix the Espresso bug for constant and dontcare output. (cherry picked from commit 46b53320e9ec09fc26d63259f1821f4234640839) Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2022-01-26Expand supported val modifiers for @public (#2365) (#2367)mergify[bot]
(cherry picked from commit 13fb4595b3b21beadaad5ba5c5d131138099d6e1) Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
2022-01-20Fix Compatibility Module io wrapping (#2355) (#2358)mergify[bot]
The new reflection based IO autowrapping for compatibility mode Modules would previously throw a NullPointerExceptions if any hardware were constructed in the Module before "val io" was initialized. The logic is now more robust for this case. Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> (cherry picked from commit 50e6099fbecc041973564514e55f67ffe069459b) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-01-20Fix link to Naming Cookbook (#2356) (#2357)mergify[bot]
#naming implies within the current file. Removing the # refers to a file in the current directory. (cherry picked from commit 512ddd6c8b079dd83f2a3ed793e6595822a382cb) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-01-19util: add GrayCode (#2353) (#2354)mergify[bot]
(cherry picked from commit 91d7baa8e7162d736f46b6d4964b09016d2dd172) Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
2022-01-17Add 3.5.x to Github Actions push triggersJack Koenig
2022-01-12Update README and PR template for 3.5.0 release (#2339) (#2342)mergify[bot]
(cherry picked from commit d6710acbb969d0608693cb53142ea485062771d2) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-01-11Set mimaPreviousArtifacts for binary compatibility checkingJack Koenig
2022-01-12Merge branch 'master' into 3.5-releaseJack
2022-01-12Bump version strings.Jack
2022-01-11Lookupable: add Either version (#2335)Megan Wachs
* Add Lookupable for Either * Lookupable: enhance the @public/@instantiable error message to include traits and Eithers Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-01-10Merge pull request #2246 from chipsalliance/scalafmtJack Koenig
Add scalafmt configuration and apply it.
2022-01-10Enable scalafmt in CIJack Koenig
2022-01-10Apply scalafmtJack Koenig
Command: sbt scalafmtAll
2022-01-10Add scalafmt config, SBT plugin, and mill supportJiuyang Liu
Can be run in two ways: * sbt scalaFmtAll * mill mill.scalalib.scalafmt.ScalafmtModule/reformatAll __.sources
2022-01-10Merge pull request #2334 from chipsalliance/update-mergify-queue-actionJack Koenig
Update mergify queue action
2022-01-10Update Mergify config for new queue actionJack Koenig
Mergify deprecated and removed strict mode in the merge action. Instead, we now use the queue action. Using ucb-bar/chisel-repo-tools#38.
2022-01-10Add config for generating .mergify.ymlJack Koenig
Generation script is chisel-repo-tools/scripts/mergify.sc
2022-01-07Add a Select.ios that works with Definition/Instance, fix isA behavior (#2315)Megan Wachs
* New Feature: Add a Select.ios that works with Definition/Instance * BugFix: isA now truly ignores type parameters
2021-12-21Update README for 3.5.0-RC2 (#2317)Jack Koenig
2021-12-20Merge pull request #2314 from chipsalliance/fix-unidocJack Koenig
Fix unidoc
2021-12-20Turn on unidoc checking in CIJack Koenig
2021-12-20[plugin] add -P:chiselplugin:INTERNALskipFileJack Koenig
This enables skipping files in the compiler plugin, only needed for unidoc generation.
2021-12-20[plugin] Internal refactor, remove useBundlePluginJack Koenig
It is always true. The scalacOption to enable it is still supported and prints a warning that the option no longer does anything.
2021-12-20Better documentation for := and <> (#2312)Olushola Ogunkelu
2021-12-18Merge branch 'master' into 3.5-releaseJack
2021-12-18Bump version strings.Jack
2021-12-18Revert "Make stuff in IR.scala package private (#2274)" (#2308)Jack Koenig
This reverts commit 21e324727e99f0bc124aaddea7fe294b4111c23a. Note that I am keeping the change making Arg sealed.
2021-12-17Improve exception message for aliased bundle fields (#2304)Chick Markley
- Shows groups of field names that share a common id (i.e. aliased) - Show, as much as possible, them in the order that fields appear in bundle - Updated BundleSpec's relevant tests Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 19:01:15 +0000