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2016-10-04Generate a better error message for missing IO() wrapper - fix #305Jim Lawson
2016-09-30clone firrtlDirection when cloningJim Lawson
2016-09-30Merge pull request #265 from ucb-bar/gsdtJim Lawson
Gsdt - Fixup to Chisel connections and direction - PR 200 revisited.
2016-09-30Merge pull request #304 from ucb-bar/gsdt-adddirmethodJim Lawson
Add Data dir method to Chisel compatibility layer.
2016-09-30Add Data dir method to Chisel compatibility layer.Jim Lawson
2016-09-29Merge branch 'gsdt-renamecompileoptions' into gsdtJim Lawson
2016-09-29Manual dead code elimination.Jim Lawson
2016-09-29Merge pull request #302 from ucb-bar/gsdt-renamecompileoptionsRichard Lin
Massive rename of CompileOptions.
2016-09-29Consolidate CompileOptions and re-enable NotStrict pending macro work.Jim Lawson
2016-09-29Massive rename of CompileOptions.Jim Lawson
Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports. NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence). We should really thread the CompileOptions through the macro system so the client's implicits are used.
2016-09-28Generate scaladoc for all subprojects.Jim Lawson
Use aggregate to run project tasks in subprojects Use sbt-unidoc to generate combined scaladoc for project and subprojects.
2016-09-28Merge pull request #299 from ucb-bar/gsdt-decoupleddirection298Jim Lawson
Don't use firrtlDirection for direction checks - fix #298.
2016-09-28Don't use firrtlDirection for direction checks - fix #298.Jim Lawson
firrtlDirection should only be used for emitting firrtl. Any checks on the actual direction should use the bound Direction `dir`.
2016-09-27Use "chisel3" as sbt project name.Jim Lawson
2016-09-26Merge pull request #295 from ucb-bar/gsdt-defaultcoJim Lawson
Add Strict default for compile options, onto gsdt
2016-09-26Add Strict default for compile optionsducky
2016-09-23Merge branch 'master' into gsdtJim Lawson
2016-09-23Merge pull request #291 from ucb-bar/utilscaladocsJim Lawson
Scaladocs for utils
2016-09-22Update rest of docsducky
2016-09-21Add Cookbook testsjackkoenig
These tests are intended to be the examples in the Chisel3 Wiki Cookbook.
2016-09-21Improved scaladoc in utils and friendsducky
2016-09-21Expose FIRRTL asClock constructAndrew Waterman
Additionally, fix Clock.asUInt (previously, it threw an esoteric exception), and add a simple test of both.
2016-09-21Use correct scope for util synonyms.Jim Lawson
2016-09-21Make implicit clock name consistent (#288)Andrew Waterman
In the Chisel frontend, the implicit clock is named clock, but in the generated FIRRTL, it is named clk. There is no reason for this discrepancy, and yet fixing it is painful, as it will break test harnesses. Better to take the pain now than later. Resolves #258.
2016-09-16Merge branch 'master' into gsdtJim Lawson
o explain why this merge is necessary,
2016-09-16Rename DecoupledIO object to Decoupled (compatibility).Jim Lawson
2016-09-15Decoupled: cast DecoupledIO to IrrevocableIO as an input (#280)Wesley W. Terpstra
2016-09-15add optional directionality assumption to BiConnect.elemConnectJim Lawson
2016-09-15move AddMethodsToDecoupled to ReadyValidJim Lawson
2016-09-15Revert "Add direction-only (no width) UInt factory method."Jim Lawson
This reverts commit 920f6dc168d8e486733666368c7e363065b685ee.
2016-09-15Add direction-only (no width) UInt factory method.Jim Lawson
2016-09-15Merge branch 'master' into gsdtJim Lawson
2016-09-13Bugfix: actually pass flow parameter from Queue factory to Queue module ↵Henry Cook
constructor
2016-09-09Convert to NotStrict for internal connection checks.Jim Lawson
2016-09-08Add IrrevocableIO alternative to DecoupledIO (#274)Henry Cook
Add IrrevocableIO subclass of DecoupledIO that promises not to change .bits on a cycle after .valid is high and .ready is low
2016-09-08Merge pull request #275 from ucb-bar/fix-printableJim Lawson
Fix bug in Printable FullName of submodule port
2016-09-07Fix bug in Printable FullName of submodule portjackkoenig
Printable was using HasId.instanceName to get full names of Chisel nodes. instanceName uses the parent module of the HasId to get the Component to use in calling fullName on the underlying Ref. Unfortunately this means that any reference to a port of a instance will leave off the instance name. Fixing this required the following: - Add Component argument to Printable.unpack so that we can call Arg.fullName directly in the Printable - Pass the currently emitting module as the Component to Printable.unpack in the Emitter - Remove ability to create FullName Printables from Modules since the Module name is not known until after the printf is already emitted This commit also updates the PrintableSpec test to check that FullName and Decimal printing work on ports of instances
2016-09-07Add Printable (#270)Jack Koenig
Printable is a new type that changes how printing of Chisel types is represented It uses an ordered collection rather than a format string and specifiers Features: - Custom String Interpolator for Scala-like printf - String-like manipulation of "hardware strings" for custom pretty-printing - Default pretty-printing for Chisel data types
2016-09-06Verify we can suppress the inclusion of default compileOptions.Jim Lawson
2016-09-02Rename implicit compileOptions to defaultCompileOptions.Jim Lawson
2016-09-02Add/cleanup UInt/SInt factory methods.Jim Lawson
2016-09-02Deprecate asBits; modify deprecation warnings accordinglyAndrew Waterman
2016-09-01Remove O(n^2) code in Vec.apply(Seq)Andrew Waterman
The O(n) type legality check was redundantly executed n times. D'oh.
2016-09-01Merge pull request #273 from ucb-bar/check-vecJim Lawson
Check that Vecs have homogeneous types
2016-09-01Deprecate Vec.fill() offering Vec(Seq.fill()).Jim Lawson
2016-09-01Move connection implicits from Module constructor to connection methods.Jim Lawson
Eliminate builder compileOptions.
2016-09-01Bump version number in preparation for release.Jim Lawson
2016-08-31Check that Vecs have homogeneous typesAndrew Waterman
Vec[Element] can have heterogeneous widths. Vec[Aggregate] cannot (but possibly could relax this by stripping widths from constituent Elements and relying on width inference).
2016-08-31Bump version number in preparation for release.Jim Lawson
2016-08-30Merge branch 'master' into gsdtJim Lawson
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