summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2017-02-28Fix minor typo in readme (#537)Siddhanathan Shanmugam
2017-02-28Use test_run_dir for more tests. (#534)Jim Lawson
* Use test_run_dir for more tests. * Use official option and DRY. Make "test_run_dir" the default for ChiselSpec. Verify output files are created in DriverSpec tests.
2017-02-27Add test for digit field names in RecordsJack Koenig
2017-02-27Record: allow elements to start with a digitWesley W. Terpstra
This is necessary for user-defined Record-derived types to retain the same signal name as they would using a Vec.
2017-02-27Update BetterNamingTests to use NamedModuleTesterJack Koenig
2017-02-24Fix mismatch between Chisel and Firrtl on UInt -& UIntJack Koenig
Fixes #501. Also added UIntOps test.
2017-02-24Test that large Vecs can have widths inferredjackkoenig
Test for ucb-bar/firrtl#407
2017-02-24Escape % in assertion messagesJack Koenig
2017-02-23Fend off future bug - replace FixedPoint ":=" with "connect". (#516)Jim Lawson
This turned up after updating #494 (Remove explicit import of NotStrict) and adding the missing implicit CompileOptions to ":="'s signature at which point Scala pointed out FixedPoint's ":=" could not override Data's final ":=" with the same signature: the implicit time bomb.
2017-02-22Bugfix #513. Fix BPSet width inference in Chisel3 (#523)Adam Izraelevitz
* Bugfix #513. Needs better test case * Improved test
2017-02-21Use chisel3 in libraryDependencies example. (#520)Jim Lawson
2017-02-17Builderreflectionfix (#515)Angie Wang
* change builder for bundle reflection fix * fixed bug -- should be not assignable
2017-02-16Add scaladoc examples for Vec and Bundle (#511)Chick Markley
* Add scaladoc examples for Vec and Bundle * address comments, added @example tag eliminate extraneous context * address comments, added @example tag eliminate extraneous context * ok, I've wrestled with the javadoc sytnax, the following commit, is my best result so far
2017-02-16Add support for clock and reset scoping (#509)Jack Koenig
withClockAndReset, withReset, and withClock allow changing the implicit clock and reset. Module.clock and Module.reset provide access to the current implicit clock and reset.
2017-02-15Blackbox comments spelling correction thanks to edwardcwangFabien Marteau
2017-02-15BlackBox documentation: adding the verilog template to generateFabien Marteau
2017-02-15Adding a BlackBox example in code documentationFabien Marteau
2017-02-15Implement asTypeOf, refactor internal APIs (#450)Richard Lin
2017-02-15Fixed point factory stuff (#505)Chick Markley
* Don't allow analog to analog monoconnect adjust tests accordingly * demonstrate bit loss in shift right for fixed point * cleaned up some stuff. this does not test clean due to bug in firrtl
2017-02-08Fix random failures in CompatibilitySpec (#498)Jack Koenig
2017-02-08Add Analog typeJack Koenig
Used for stitching Verilog inout through Chisel Modules (from BlackBox to BlackBox)
2017-02-08Add counter for depth of when scopeJack Koenig
2017-02-08Fix up deprecation warnings and clean up CompatibiltySpec code. (#471)Jim Lawson
There was some dubious (certainly unclear) code organization in the CompatibiltySpec tests. The isPow2() test was randomly failing in Jenkins builds. This may address the problem.
2017-02-08Bump sbt version.Jim Lawson
2017-02-07Fix up Absolute value #abs (#491)Chick Markley
* Fix up Absolute value #abs Defines #abs in Num Implement #abs in UInt Change #abs in SInt to return an SInt Change #abs in FixedPoint to return a FixedPoint Added a couple of tests Add some scala style suppression to Bits so I can read code in IntelliJ * Per review Add tests that abs works for positive values Added SInt and UInt tests for abs to new underpopulated IntegerMathSpec Used fixed point literals in fixed points abs definition
2017-02-07Add generateFirrtl() method to ChiselSpec.scala (#423)Jim Lawson
2017-02-07Name all the thingsducky
2017-02-07Add macro for compile options materialize to prevent its use in chisel coreducky
2017-02-07Rename SeqMem to SyncReadMem. (#490)Jim Lawson
Retain un-deprecated SeqMem in compatibility mode, deprecate in chisel3.
2017-02-03Added vec IO tests for #104 (#480)Jim Lawson
* Added vec IO tests for #104 * Added Vec test case for Reg of vecs * Change Vec creation to check if gen is lit (and hence needs to be declared) Fixes #104 * Fix tests (add IO())), Vec.fill() * Fix deprecated usage. * Add Binding IO() NPE fix so tests pass. * Fix style - use space consistently. * Fix style - use space consistently.
2017-02-03Fix potential NPE if we try to evaluate isMissingIOWrapper() inside IO(). (#479)Jim Lawson
2017-02-02Revamp VendingMachine.scala as cookbook examplejackkoenig
* Move to cookbook * Change FSM implementation to use switch & is * Add non-FSM implementation * Add execution-driven test
2017-02-02Bring cookbook up to date with chisel3 APIjackkoenig
2017-02-01Move backend compilation utilities (#400)Jim Lawson
* Move copyResourceToFile() to BackendCompilationUtilities. * Move BackendCompilationUtilities into a firrtl util package. Some of this could be moved into a more general tools package, but since chisel3 already has a dependency on firrtl ... * Push util down into firrtl so as not to conflict with scala.util. * Use new createTestDirectory. Fixes #452.
2017-01-31fix buildInfoPackage name (and comment)Jim Lawson
2017-01-31Make Module and Bundle properly use empty namespacesJack
Fix default suggested name of Module instances (now based on desired name rather than actual assigned name). Remove parent/child relationship from Namespace. Previously, Module and Bundle namespaces were "children" of the Module definition namespace. This could lead to collisions that would give unexpected names for module instances or Bundle elements. In particular, otherwise identical modules that instantiate other identical modules in such a way that the instance cannot be named via reflection would not be deduplicated because the names of the instances would collide with the names of the modules in the Builder.globalNamespace.
2017-01-31Add compile [to Verilog] to ChiselRunnersJack
2017-01-31Fix spelling of ChiselExecutionSuccessJack
2017-01-31Move blackbox verilog implementations within reach of verilator (#453)Chick Markley
* Move blackbox verilog implementations within reach of verilator Blackbox implementers can annotate the modules with information on where to get the source verilog This API is very lightweight, real work is done in firrtl in companion PR Added some verilog to BlackBoxTest.v resource for testing * if a file named black_box_verilog_files.f exists add a -f black_box_verilog_files.f to the verilog to cpp command
2017-01-30Add shift register with reset (#439)Stevo
* [stevo]: add reset initialization to shift register * [stevo]: better comment * [stevo]: add tests, fix bug
2017-01-27Add pointer to ScalaDoc. (#397)Jim Lawson
2017-01-27Deprecate firrtlToVerilog in favor of compileFirrtlToVerilog (#367)Jack Koenig
Resolves #357 Also remove uses of firrtlToVerilog within chisel3. Invoking Firrtl programmatically is preferred to on the command line. Update README to indicate that Firrtl need not be installed.
2017-01-27Make uselessly public fields in utils privatejackkoenig
2017-01-27Clean names of private vals in Modulesjackkoenig
2017-01-27Add basic Chisel2 compatibility sanity checks. (#340)Jim Lawson
2017-01-27Have checkpoint report (and clear) non-fatal errors. (#376)Jim Lawson
2017-01-27Provide package-level text to reduce ScalaDoc white space. (#432)Jim Lawson
2017-01-26Change definition of root project to minimize potential confusion.Jim Lawson
2017-01-26Use the same firrtl for all sub-projects.Jim Lawson
Use the root project's unmanagedBase (".../lib") in all sub-projects.
2017-01-26doesn't lose old firrtl options annotations + transforms (#458)Angie Wang
Fixing a bug in passing down execution options to firrtl
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-12 03:34:19 +0000