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2018-09-07Add UInt ScalaDoc documentationSchuyler Eldridge
This adds documentation of Arithmetic, Comparison, and Bitwise operator methods of UInt. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-09-07Add Num ScalaDoc documentationSchuyler Eldridge
This includes general documentation for the arithmetic and comparison operators of Num. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-09-07Add Bits ScalaDoc documentationSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-09-07Put := and <> methods in Connect ScalaDoc groupSchuyler Eldridge
This puts Data's connection methods, `:=` and `<>`, in the ScalaDoc `Connect` group. These groups will propagate through to all children of Data, e.g., UInt, and cause those methods to be grouped in the ScalaDoc of these children. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-09-07Put do_* methods in SourceInfoTransformMacro groupSchuyler Eldridge
This places all do_* methods (and two unary methods in SInt and FixedPoint that act like do_* methods) inside the ScalaDoc group "SourceInfoTransformMacro". Classes/objects which need information about this group have an additional bare trait mixed in, `SourceInfoDoc`, that provides information about the group and its priority. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-09-07Enable ScalaDoc groups, ignore chisel3.internalSchuyler Eldridge
This adds the `-groups` option to `scalacOptions`. This makes ScalaDoc build with group support such that developers can group methods using the `@group <groupName>` tag. This also adds the `-skip-packages chisel3.internal` option. This makes ScalaDoc build while ignoring everything in the chisel3.internal package. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-09-07Add Logical ScalaDoc group to NumSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-09-07Add Comparison ScalaDoc group to NumSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-09-07Add Arithmetic ScalaDoc group to NumSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-09-07Add Bitwise ScalaDoc group to BitsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-09-07Add Connect ScalaDoc group to DataSchuyler Eldridge
This adds the ScalaDoc group "Connect" to the Data class. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-09-07Add SourceInfoDoc trait w/ ScalaDoc groupSchuyler Eldridge
This adds a bare trait that provides a ScalaDoc group, `SourceInfoTransformMacro`, that is intended to group all `do_*` methods in one place in the documentation. This provides a group description for this group and a priority (1001) which is lower than all other normal groups (the lowest priority is supposed to be 1000). Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-09-07Bump scopt from 3.6.0 -> 3.7.0 (#877)Schuyler Eldridge
This bumps scopt from 3.6.0 to 3.7.0 to align with FIRRTL. FIRRTL requires 3.7.0+ for added scopt methods that allow introspection of options (e.g., examing the short options of a long option). This bump avoids a compile-time warning due to the version mistmatch. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-08-31Support for verilog memory loading. (#840)Chick Markley
* Ability to load memories at simulation startup * first pass * create annotation * create skeleton Transform * Work in progress Building out transform and pass now * Support for LoadMemory annotation * Creates chisel and firrtl LoadMemory annotations * LoadMemoryTransform converts annotation into BlackBox InLine * Simple test that verilog bound modules get created. * Support for LoadMemory annotation * Supports Bundled/multi-field memories * more tests * support for `$readmemh` and `$readmemb` * warns if suffix used in file specification. * Support for LoadMemory annotation * Use standard chisel annotation idiom * Support for LoadMemory annotation * Fixes for @seldridge nits and super-nits * Support for LoadMemory annotation - transform now only runs if emitter is an instance of VerilogEmitter - suffixes on memory text files are now respected - if suffix exists and memory is aggregate, aggregate sub-fields will now be inserted before suffix - every bind module created gets a unique number - this is required when multiple loaded memories appear in a module - this should be generalized for other uses of binding modules * Support for LoadMemory annotation - remove un-needed suffix test * Support for LoadMemory annotation - remove instance walk, now just processes each module * Support for LoadMemory annotation - Move LoadMemoryTransformation into Firrtl for treadle to access it. * Support for LoadMemory annotation - One more bug in suffix handling has been eliminated * Support for LoadMemory annotation - remove unused findModule per jackkoenig - fixed complex test, bad filename edge case * Support for LoadMemory annotation - changed to not use intellij style column alignment for : declarations * Load memory from file Fixes based on @jkoenig review - remove unused BindPrefixFactory - Moved code from CreateBindableMemoryLoaders into to LoadMemoryTransfrom - Made map to find relevant memory annotations faster - Made map to find modules referenced by annotations faster - Made things private that should be private - DefAnnotatedMemorys are no longer referenced, shouldn't be found here. - println of error changed to failed * Loading memories from files - Many changes based on review - move stuff into experimental - clean up annotation manipulation - manage tests better - use more standard practices for transform * Loading memories from files - More review changes - Move doc from annotation to the object apply method that generates the annotation - Make scalastyle directives more specific - Use more efficient collect to generate name to module map - Made lines obey style length limit - a couple of cleanups of imports in tests - removed some commented out code - optimized checking for lines using .exists - use _ for unused variable in match
2018-08-29Inhibit aggressive resource file name mangling. (#884)Jim Lawson
* Inhibit aggressive resource file name mangling. This addresses #883. * Use common method to write resources to a directory to keep file names consistent.
2018-08-23Merge pull request #838 from seldridge/issue-602Jack Koenig
Add instance inline API
2018-08-23Add FlattenInstance APISchuyler Eldridge
This adds a new trait, FlattenInstance, to chisel3.util.experimental. When mixed into a module or a specific instance this trait will "flatten", i.e., "inline that module and all of its submodules". This includes testing (additions to InlineSpec) and ScalaDoc documentation. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-08-23Add InlineInstance APISchuyler Eldridge
This adds a new trait, InlineInstance, to chisel3.util.experimental. This trait, when mixed into a specific module or instance, will "inline" that module, i.e., "collapse a module while preserving it's submodules." This includes testing (InlineSpec) and ScalaDoc documentation. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-08-22Update class name in error messageEdward Wang
2018-08-22Implement varargs MixedVec APIEdward Wang
2018-08-22Make MixedVec wire init consistent with VecInitEdward Wang
2018-08-22Remove dynamic indexing for nowEdward Wang
We can sometimes shim with other workarounds like VecInit or manually creating a mux
2018-08-22Use a mix-in to override Seq errorEdward Wang
2018-08-22MixedVec: clarify dynamic indexing of heterogeneous elementsEdward Wang
2018-08-22Warn user that using Seq for hardware construction in Bundle is not supportedEdward Wang
2018-08-22Remove redundant := methodEdward Wang
2018-08-22MixedVec implementationEdward Wang
2018-08-22Minor tweaks to the style guide (#876)edwardcwang
2018-08-21Bump to Scala 2.12.6 and make it the default. (#858)Jim Lawson
2018-08-07BoringUtils / Synthesizable Cross Module References (#718)Schuyler Eldridge
This adds an annotator that provides a linkage to the FIRRTL WiringTransform. This enables synthesizable cross module references between one source and multiple sinks without changing IO (the WiringTransform bores through the hierarchy). Per WiringTransform, this will connect sources to their closest sinks (as determined by BFS) or fail if ownership is indeterminate. Make TesterDriver.execute work like Driver.execute: - annotations are included when running FIRRTL - custom transforms are run automatically Also, add a bore method to BoringUtils that allows you to do one source to multi-sink mapping in a single call. This adds a test that this is doing the same thing as the equivalent call via disjoint addSink/addSource. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-07-31Cleanup implicit conversions (#868)Jack Koenig
2018-07-31Ensure names work for bundles and literals. (#853)Jim Lawson
Fixes #852
2018-07-31Revert removal of bit extraction const prop for literals (#857)Jack Koenig
See https://github.com/freechipsproject/chisel3/issues/867 for future API discussion
2018-07-26Update latest release. (#863)Jim Lawson
2018-07-19Add support for Input() and Output() (available in Chisel2 since ↵Jim Lawson
ucb-bar/chisel2-deprecated#734) and test for same.
2018-07-11Update versions and links in README (#855)Jack Koenig
2018-07-10Fix use of read-only refs on rhs of connect in compatibility mode (#854)Jack Koenig
2018-07-09Bump recommended Verilator version to 3.922 (#851)Jim Lawson
2018-07-06Undeprecate log2Up and log2Down (#846)Jack Koenig
They should not be deprecated until zero-width wires actually work
2018-07-05Ignore eclipse temporariesRichard Lin
2018-07-04Change wording of internal failureRichard Lin
2018-07-04Fix strict namerRichard Lin
2018-07-04Remove forceName rom BlackBox/ExtModule, filter out forceName in UserModuleRichard Lin
2018-07-04Add test that UInt, SInt, and FP literals do not impact namingJack Koenig
2018-07-04Prefer litValue, eliminate litToBigIntducky
2018-07-04Change [public] Data.elementLitArg => [protected] Aggregate.litArgOfBitsducky
2018-07-04Style fixesducky
2018-07-04binding => topBinding so that partial Bundles work and undefined Bundle ↵ducky
members properly forward to DontCareBinding
2018-07-04properly fix undefined clock/reset issuesducky
2018-07-04Add BundleLiteralSpecRichard Lin
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