summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2022-06-27Deprecate TransitName (backport #2603) (#2606)mergify[bot]
* Deprecate TransitName (#2603) * Deprecate TransitName * Add @nowarn macros to usages of TransitName in the repo Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit a0b05190e5303ec28a0c7abe645d81e9a72023ff) * Update src/main/scala/chisel3/util/Valid.scala * Update src/main/scala/chisel3/util/Valid.scala Co-authored-by: Megan Wachs <megan@sifive.com>
2022-06-23Publish unidoc as ScalaDoc in chisel project (backport #2595) (#2598)mergify[bot]
* Publish unidoc as ScalaDoc in chisel project (#2595) This makes it such that we can stop hosting ScalaDoc on the Chisel website, instead just pointing to the latest docs on javadoc.io (cherry picked from commit 8b9f3d78ea23d9d9f0a118d1a2c30478ca2ff2f9) # Conflicts: # build.sbt * Resolve backport conflicts Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2022-06-23Add DataMirror isIO, isReg, isWire (#2601) (#2602)mergify[bot]
(cherry picked from commit 7fa0d8bf1cafcdf141046476a100abf021bdcac4) Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
2022-06-22README: fix link to contributing.md (#2596) (#2600)mergify[bot]
Co-authored-by: Megan Wachs <megan@sifive.com> (cherry picked from commit 4da410e09263ac6cdafce63858ee2f4c552e914f) Co-authored-by: Michael Etzkorn 叶明凯 <34870910+metzkorn@users.noreply.github.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2022-06-22Replace verilog code with pre-formatted HTML to avoid breaking website ↵mergify[bot]
(#2593) (#2599) (cherry picked from commit 6ecf4d39d413a7d955a8b358cb34685aaefed1a2) Co-authored-by: Carlos Eduardo <me@carlosedp.com>
2022-06-22Pass optional name in ImportDefinitionAnno (#2592) (#2594)mergify[bot]
Used for separate elaboration of Definition and Instance (cherry picked from commit 48d57cc8db6f38fdf0e23b7dce36caa404c871b8) Co-authored-by: Girish Pai <girish.pai@sifive.com>
2022-06-21Make readme friendlier to beginners (backport #2586) (#2590)mergify[bot]
* Make readme friendlier to beginners (#2586) (cherry picked from commit 773d2d675dd0c1697b8daeab67755834c0a9c735) # Conflicts: # README.md * Resolve backport conflicts Co-authored-by: Carlos Eduardo <me@carlosedp.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-06-18Handle varargs constructor arguments in Bundle plugin (#2585) (#2588)mergify[bot]
Previously, the plugin would crash with a useless internal error. (cherry picked from commit 9fcfb252beb9f06d8d1409fe7db9c8b3b6b962ce) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-06-17[docs] Document partial register reset (#2582) (#2583)mergify[bot]
(cherry picked from commit d54a37a51b16fb6e46093265d65fd47d5318f67f) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-06-16Define leading '_' as API for creating temporaries (backport #2580) (#2581)mergify[bot]
* Define leading '_' as API for creating temporaries Chisel and FIRRTL have long used signals with names beginning with an underscore as an API to specify that the name does not really matter. Tools like Verilator follow a similar convention and exclude signals with underscore names from waveform dumps by default. With the introduction of compiler-plugin prefixing in Chisel 3.4, the convention remained but was hard for users to use unless the unnnamed signal existed outside of any prefix domain. Notably, unnamed signals are most useful when creating wires inside of utility methods which almost always results in the signal ending up with a prefix. With this commit, Chisel explicitly recognizes signals whos val names start with an underscore and preserve that underscore regardless of any prefixing. Chisel will also ignore such underscores when generating prefixes based on the temporary signal, preventing accidental double underscores in the names of signals that are prefixed by the temporary. (cherry picked from commit bd94366290886f3489d58f88b9768c7c11fa2cb6) * Remove unused defaultPrefix argument from _computeName (cherry picked from commit ec178aa20a830df2c8c756b9e569709a59073554) # Conflicts: # core/src/main/scala/chisel3/Module.scala # core/src/main/scala/chisel3/experimental/hierarchy/ModuleClone.scala * Resolve backport conflicts * Waive false positive binary compatibility errors Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-06-13Add ImplicitInvalidate, to help migrate the explicitInvalidate compiler ↵mergify[bot]
option (#2575) (#2579) * Added ImplicitInvalidate trait with tests (cherry picked from commit 1356ced1b89ca35ae0cb1d1ab45227ec1776d5e7) Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
2022-06-11Micro-optimize BitPat.rawString (#2577) (#2578)mergify[bot]
BitPat.rawString is called a lot when decoding and is used for certain BitPat operations. We should use it less but this is at least a bandaid. (cherry picked from commit c11af20fe5b211ec72ba00f3ce0880d7933e566b) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-06-08Added migration for inferModuleReset (#2571) (#2573)mergify[bot]
Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 3c6c044b6bdee850ad9ba375324abaf3813c557d) Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
2022-06-08Enhance suggestion in literal extract warning (#2569) (#2570)mergify[bot]
Include the function being called in the suggestion. (cherry picked from commit 296623f6f41eb9f54899277621902679bb6b497c) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-06-07Add single argument Bits.extract (#2566) (#2568)mergify[bot]
(cherry picked from commit 255c56c3955a8c16191a6751e7d547cfcfd96705) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-06-06Add --warn:reflective-naming (backport #2561) (#2565)mergify[bot]
* Factor buildName into reusable function The new function is chisel3.internal.buildName. (cherry picked from commit 370ca8ac68f6d888dd99e1b9e63f0371add398cf) * Add --warn:reflective-naming This new argument (and associated annotation) will turn on a warning whenever reflective naming changes the name of a signal. This is provided to help migrate from Chisel 3.5 to 3.6 since reflective naming is removed in Chisel 3.6. (cherry picked from commit 97afd9b9a1155fa7cd5cedf19f9e0c15fbe899ec) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-06-03Deprecate implicit .U() and .S() syntax for literal bit extracts (backport ↵mergify[bot]
#2534) (#2559) * Deprecate .U() and .S() syntax for literal bit extracts (#2534) (cherry picked from commit cadaf33a650ef898fdab2f81244e4ad6a07a9ea8) # Conflicts: # macros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala * Fix backport conflict (#2560) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-06-02Support VerificationStatement in the naming plugin (#2555) (#2557)mergify[bot]
Previously, verification statements (assert, assume, cover, and printf) were only named via reflection. (cherry picked from commit 7fa2691f670813eef4ec59fc27c4e4f625d598de) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-06-01Add formatted Printable interpolator `cf` (#2528) (#2553)mergify[bot]
This is a formatted version of the p"..." interpolator analogous to Scala's f"..." interpolator. The primary difference is that it supports formatting interpolated variables by following the variable with "%<specifier>". For example: printf(cf"myWire = $myWire%x\n") This will format the hardware value "myWire" as a hexidecimal value in the emitted Verilog. Note that literal "%" must be escaped as "%%". Scala types and format specifiers are supported and are handled in the same manner as in standard Scala f"..." interpolators. (cherry picked from commit 037f7b2ff3a46184d1b82e1b590a7572bfa6a76b) Co-authored-by: Girish Pai <girish.pai@sifive.com>
2022-05-29Deprecate accessing the name of non-hardware Data (#2550) (#2552)mergify[bot]
This includes (and is tested) for both the old .*Name APIs and .toTarget (cherry picked from commit 6e0d8d6b12e9d8f94c2cc43b92b2366ec70dfd50) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-27Make ExtModule port naming consistent with Module (#2548) (#2549)mergify[bot]
ExtModule now uses the same namePorts implementation as regular Modules. Previously, ExtModules only allowed port naming via runtime reflection. This meant that .suggestName and other naming APIs do not work. It also breaks FlatIO for ExtModule which is a potential replacement API for BlackBox's special `val io` handling. (cherry picked from commit 83cccfb782d9141bf2c843246c2a525c62392924) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-24Support Vecs of empty Bundles (#2543) (#2545)mergify[bot]
(cherry picked from commit a1e3a6b5324997864168111bee8c02a60abb0acc) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-19Support := views to DontCare (#2536) (#2539)mergify[bot]
(cherry picked from commit 77a6c93592d5766d66f199720fc6d69478005091) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-19Update experimental-features.md (#2537) (#2538)mergify[bot]
(cherry picked from commit 68510515467ef7a86c54b2e710bfc5e736f7a2aa) Co-authored-by: Gonsolo <gonsolo@gmail.com>
2022-05-14Deprecate named arguments for methods moving to macros in 3.6 (#2530)Jack Koenig
These methods will start using def macros and since def macros do not supported named arguments this will be a source-incompatible change. This deprecation will warn users that they need to remove any uses of named arguments on these methods.
2022-05-13Update mimaPreviousArtifacts to 3.5.3 (#2529)Jack Koenig
2022-05-12Update CONTRIBUTING.md for backport cleanup process (backport #2523) (#2524)mergify[bot]
* Update CONTRIBUTING.md with backport cleanup process (#2523) (cherry picked from commit ac19ff70458959e795933c7aad6bab88a16fcf5d) # Conflicts: # CONTRIBUTING.md * Resolve conflicts Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-12Support separately elaborating definition and instance in ChiselStage ↵mergify[bot]
(backport #2512) (#2520) * Support separately elaborating definition and instance in ChiselStage (#2512) (cherry picked from commit a0aa4d1550e3fbde199a98529cffeb176fb4bed8) # Conflicts: # core/src/main/scala/chisel3/experimental/hierarchy/Definition.scala # core/src/main/scala/chisel3/experimental/hierarchy/Instance.scala # core/src/main/scala/chisel3/internal/Builder.scala * fixing imports (#2522) Co-authored-by: Deborah Soung <debs@sifive.com>
2022-04-26Merge branch '3.5.x' into 3.5-releaseJack
2022-04-26Bump version strings.Jack
2022-04-26Fix spurious warning from Bundle plugin (#2506) (#2507)mergify[bot]
For traits or abstract classes that extend Bundle but have no concrete methods, the plugin will print a benign warning that the user cannot fix. It will no longer print that warning. (cherry picked from commit ed4a98188ee1fe43efbd3a1ba43a657a128764d6) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-04-25Fix error message for BlackBox without val io <: Record (#2504) (#2505)mergify[bot]
(cherry picked from commit f9aee1f72744abc6ee13aafc4d1a51a2783cbab8) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-04-25Fix warning injected into user code by @chiselName (#2500) (#2503)mergify[bot]
In Scala 2.13, Auto-application to `()` is deprecated. Any nullary method (ie. a method with no arguments) that is defined with () must now be called with (). @chiselName used to inject a case of this warning into user code which would then cause a warning on the @chiselName macro that the user has no way to fix. (cherry picked from commit ca902680df772445371e6c3dd907c01113afb1f5) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-04-20Generate a balanced tree with reduceTree (#2318) (#2499)mergify[bot]
The difference in logic depth for various paths now has a maximum of 1. Also make treeReduce order the same for 2.12 and 2.13 .grouped(_) returns an Iterator .toSeq on an Iterator returns a Stream in 2.12 and a List in 2.13 This can lead to changes in order when bumping from 2.12 to 2.13 that can be avoided by simply using an eager collection explicitly. Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 6975f77f3325dec46c613552eac663c29011a67c) Co-authored-by: Martin Schoeberl <martin@jopdesign.com>
2022-04-19Allow creating memories without an implicit clock (#2494) (#2495)mergify[bot]
Fixes #2470 (cherry picked from commit 44165a259bb16733a41798edca6b554b13f1d54a) Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
2022-04-19verification: switch order of assert/assume and printf (#2484) (#2493)mergify[bot]
This is a quick fix for issue #2408 (cherry picked from commit d4ef9a96c4131252a0a49002a28be3391eb67258) Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
2022-04-18Fix small typos in doc comment (#2490) (#2492)mergify[bot]
(cherry picked from commit 52165fe2796d08c664069c148868aedc64ea3777) Co-authored-by: Lucheng Zhang <79909456+geekLucian@users.noreply.github.com>
2022-04-18Clarify example in Printable (#2454) (#2456)mergify[bot]
(cherry picked from commit d6a357d29cfa7120b3c0c90684b33be1863e5599) Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2022-04-15Enable Clock Invalidation (#2485) (#2487)mergify[bot]
Loosen restrictions on clocks to enable them to be connected to DontCare, i.e., be invalidated. Co-authored-by: Jack Koenig <koenig@sifive.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 5d8a0c8e406376f7ceda91273fb0fa7a646865aa) Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2022-04-12Optimize memory use of naming prefixes (#2471) (#2480)mergify[bot]
* Use a single field instead of two in HasId (4-bytes per HasId) * Set the prefix to Nil after setting ref to free up memory Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 3aa179f0dc1a29403fd25be7d3dc08630976d018) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-04-12Enhance views to [sometimes] support dynamic indexing and implement FlatIO ↵mergify[bot]
(backport #2476) (#2479) * Capture 1:1 mappings of Aggregates inside of views This is implemented by including any corresponding Aggregates from the DataView.mapping in the AggregateViewBinding.childMap (which is now of type Map[Data, Data]). This enables dynamically indexing Vecs that are themselves elements of larger Aggregates in views when the corresponding element of the view is a Vec of the same type. It also increases the number of cases where a single Target can represent part of a view. (cherry picked from commit 1f6b1ca14ccf86918065073c3f6f3626dd83a68e) * Add FlatIO API for creating ports from Bundles without a prefix (cherry picked from commit 772a3a1fe3b9372b7c2d7cd2d424b2adcd633cdb) * [docs] Add FlatIO to the general cookbook (cherry picked from commit b4159641350f238f0f899b69954142ce8ee11544) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-04-05Micro-optimize Namespace.name (#2474) (#2475)mergify[bot]
* During sanitize, only filter the String if needed * Do not recurse on name, saving an unnecessary call to sanitize (cherry picked from commit 559b3df3e5bd6c73588638aa44a6df1244a11a53) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-04-05Micro-optimize String building in _computeName (#2472) (#2473)mergify[bot]
(cherry picked from commit 3940136bec72fc44e40d454f2c2dcc421fc92d82) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-04-01Prevent FIRRTL bulk connects on BlackBox Bundles. (#2468) (#2469)mergify[bot]
(cherry picked from commit 4da1e89f3a0b79adcb39ea5defb393ed6c00fa2f) Co-authored-by: fzi-hielscher <47524191+fzi-hielscher@users.noreply.github.com>
2022-03-30Use var List instead of ListBuffer to save memory (#2465) (#2467)mergify[bot]
This reduces memory use of every HasId by 64 bytes. Every instance of HasId (including all Data) had 2 ListBuffer vals for recording post-naming hooks, yet this feature is almost never used. These are now vars of type List which allows the common case of Nil to add no incremental memory use per instance of HasId. (cherry picked from commit cf410180ac8de854d8d7ecf89f4813ac8541dcdb) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-03-25rm unused/deprecated BlackBoxResourceAnno import (#2458) (#2460)mergify[bot]
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> (cherry picked from commit 2c2d72ceaa494b6acc351ff4300dbb40d4a7d863) Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2022-03-15Merge branch '3.5.x' into 3.5-releaseJack
2022-03-15Bump version strings.Jack
2022-03-15[docs] Add Cookbook section on aliased Bundle fields (#2444) (#2448)mergify[bot]
(cherry picked from commit d4dd21191c63a3b125193a7ffb83d478aa945d5a) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-03-10Emit FIRRTL bulkconnects whenever possible (#2381) (#2440)mergify[bot]
Chisel <> semantics differ somewhat from FIRRTL <= semantics, so we only emit <= when it would be legal. Otherwise we continue the old behavior of emitting a connection for every leaf-level Element. Co-authored-by: Deborah Soung <debs@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 3553a1583403824718923a6cc530cec3b38f5704) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 13:22:43 +0000