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signalName -> instanceName
SignalId -> InstanceId
Based on Stephen's comments on PR
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Removed extraneous logic
Renamed doStuff to buildAnnotatedCircuit
Removed println's
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generation of annotations in a chisel circuit that could be used by custom firrtl passes
This spec also shows and tests in a limited way the new API of .signalName, .pathName, parentModName which allows access to the various path information of a chisel component (something that subclasses SignalId, most prominently SubClasses of Data and Module
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* signalName: returns the chirrtl name of the signal
* pathName: returns the full path name of the signal from the top module
* parentPathName: returns the full path of the signal's parent module instance from the top module
* parentModName: returns the signal's parent **module(not instance)** name.
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* Make "def width" a private API; expose isWidthKnown instead
Resolves #256.
Since width was used to determine whether getWidth would succeed, I added
def isWidthKnown: Boolean
but another option would be to expose something like
def widthOption: Option[Int]
...thoughts?
* Document getWidth/isWidthKnown
* Add widthOption for more idiomatic Scala manipulation of widths
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The API allowed this before, but not safely, as users could create
name conflicts. This exposes the pre-deduplication/sanitization
naming API, and closes the other one.
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It's not entirely clear what the FIRRTL implementation supports, so
I'm using the ANSI C requirements for the time being.
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This has been deprecated for a long time now (and really shouldn't
have existed to begin with).
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Deprecating toBits removes the capability to cast an arbitrary
type to UInt. While it's still possible to do so using asBits.asUInt,
this creates boilerplate. (asBits is almost never useful itself.)
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For Chisel nodes defined in Module class-level values of type Option or
Iterable, we can still use reflection to assign names based on the name
of the value. This works for arbitrary nesting of Option and Iterable so
long as the innermost type is HasId. Note that this excludes Maps which
always have an innermost type of Tuple2[_,_].
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Clean up Scala code, and use +& to generate a lot less FIRRTL
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For reasonable circuit delay, need to divide & conquer.
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Closes #229
h/t @sdtwigg @davidbiancolin
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renamechisel3 - "chisel" -> "chisel3"
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(#223)
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Rather than using a global counter, memoize the last returned value for
colliding names to generate smaller sequence numbers.
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Rename package Chisel to chisel, add Chisel package for compatibility
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package/folder, move more things into utils
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Move more publishing definitions into commonSettings.
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This should have been part of PR #194.
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Add a hack to build.sbt to allow local publishing
We're merging this despite the failing tests (Jenkins ghprb isn't communicating with GitHub following security and authentication updates). We'd prefer to package all the sbt subprojects in a single jar, but current attempts to do so fail. See #208.
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Until we sort out how to include the subproject classes in a single jar file, we need to explicitly publish all subprojects.
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* chiselTests: include an example of two empty Vectors killing FIRRTL
* Aggregate: fix a bug whereby Vec[T] was using equals/hashCode of Seq
In Chisel, two vectors are NOT equal just if their contents are equal.
For example, two empty vectors should not be considered equal. This
patch makes Vec use the HasId._id for equality like other Chisel types.
Without this fix, Bundle.namedElts.seen: HashSet[Data]() will eliminate
one of the named vectors and emit bad IR.
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