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2019-01-22Merge pull request #978 from seldridge/boring-utils-dedup-fixSchuyler Eldridge
- Fix BoringUtils deduplication bug, include new tests - Update/clarify BoringUtils scaladoc
2019-01-22Changes to BoringUtils Scaladoc, paramater nameSchuyler Eldridge
This compresses the Scaladoc for BoringUtils slightly by using 120 character lines and removing unnecessary whitespace. This also changes the poorly named "dedup" parameter to the what it actually is: "disableDedup". Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-01-22Fix BoringUtilsSpec to require no dedupSchuyler Eldridge
This adds two tests to the BoringUtilsSpec to explicitly verify that deduplication is required when boring. This adds tests that both verify that the test passes as expected with deduplication enabled and that the same test fails with deduplication disabled. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-01-22Fix BoringUtils deduplication bugSchuyler Eldridge
This fixes a bug where BoringUtils non-hierarchical sinks would be deduplicated even when specified that they should not be. h/t @ucbjrl for discovering this! Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-01-22Add Rocket Chip-style clonemodule as CloneModuleAsRecord to experimental (#943)Albert Magyar
2019-01-21Support DontCare in Mux and cloneSupertype (#995)Richard Lin
2019-01-21Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) ↵Richard Lin
Module class names (#994)
2019-01-18Remove bin (#991)Richard Lin
2019-01-17Merge pull request #987 from freechipsproject/unary-not-fixSchuyler Eldridge
Fix scaladoc for UInt.unary_!
2019-01-17Unary_- is truncatingAndrew Waterman
2019-01-17Make combinational-multiplier warning less vagueAndrew Waterman
2019-01-17Improve description of UInt.asSIntAndrew Waterman
2019-01-17Fix width-inference description of Bits.<<Andrew Waterman
2019-01-17Fix scaladoc for UInt.unary_!Andrew Waterman
It performs the operation (x === 0.U), just like in C. The scaladoc incorrectly described it as performing the operation !x(0). (Obviously, these are equivalent for Bool, but not for UInt in general).
2019-01-17Merge pull request #988 from freechipsproject/improve-andrSchuyler Eldridge
Generate better code for UInt.andR
2019-01-17Merge branch 'master' into improve-andrSchuyler Eldridge
2019-01-17Generate better code for UInt.andRAndrew Waterman
In the case that the width is known, we can emit one fewer Firrtl node. This obviously synthesizes the same way, but compiles/simulates faster.
2019-01-11Add test for chiselNaming of Seq[Data]Andrew Waterman
2019-01-11For chiselName, use nameRecursively rather than matching on HasIdAndrew Waterman
2019-01-11Move nameRecursively into Builder so it can be used elsewhereAndrew Waterman
2019-01-09Merge pull request #979 from seldridge/procedural-wire-assignmentSchuyler Eldridge
Avoid procedural wire assignment in test resource
2019-01-09Avoid procedural wire assignment in test resourceSchuyler Eldridge
Verilator 4.008 dropped the hammer on procedural wire assignment to align with the IEEE standard (first I've heard of this, though). The VerilogVendingMachine.v test resource will error in Verilator 4.008 with a PROCASSWIRE error if you try to compile it. This fixes that example to only assign to a register. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-01-07Fix build error due to scala bug #11125 (#967)Nick Hynes
JDK 11 `java.lang.String#lines` conflicts with Scala `StringOps#lines`. This has been fixed in scalac 2.12.8 but projects using 2.11 in their cross-build need the `Predef.augmentString` patch. [Scala bug & fix reference](https://github.com/scala/bug/issues/11125)
2019-01-07Add explicit Sonatype resolvers so SNAPSHOTs can be found remotely. (#975)Jim Lawson
**NOTE**: A `publishLocal` should replace the downloaded `.ivy2/cache/...` version with a pointer to the `.ivy2/local/...` version. To force refetching of the Sonatype repository version, you should delete both `.ivy2/{cache,local}/...` versions.
2018-12-23Add Windows setup instructions to readme (#964)Richard Lin
2018-12-19Fix width inferencing issue (#952)Jack Koenig
* Fix width propagation of non-literals in WireInit and RegInit * Change .getWidth to throw an exception instead of calling .get * Add utilities for checking inferred vs. known widths * Add tests for Wire, WireInit, Reg, and RegInit width inference * Add ScalaDoc for Reg, Wire, RegInit, and WireInit
2018-12-11Merge pull request #961 from freechipsproject/subwrapSchuyler Eldridge
Improve quality of code generation for UInt.-%
2018-12-11Emit UInt.-% as tail(sub(x,y),1), not tail(asUInt(sub(x,y)),1)Andrew Waterman
This is semantically equivalent, but gets rid of a bunch of Firrtl text. It also gets rid of a bunch of Verilog, because Firrtl is capable of pattern-matching the new expression into SubWrap. The effect is that we now get wire [4:0] in; wire [4:0] res; assign res = 5'h0 - in; instead of wire [4:0] in; wire [5:0] _T_40; wire [5:0] _T_41; wire [4:0] res; assign _T_40 = 5'h0 - in; assign _T_41 = $unsigned(_T_40); assign res = _T_41[4:0];
2018-12-06Bump SBT from 1.2.6 to 1.2.7 to fix partial recompilation issue (#956)Jack Koenig
2018-12-04Merge pull request #950 from freechipsproject/as-boolsJack Koenig
asBools, asBool, and chained apply on asBools
2018-12-04Add asBool, deprecate toBoolJack Koenig
2018-12-04Add asBools, deprecate toBoolsJack Koenig
2018-12-04Make toBools support chained applyJack Koenig
The expanded version substituted in by the macro was misspelled, renamed from toBools -> do_toBools as expected by the macro
2018-11-26Trim Stack Trace (#931)Albert Chen
- Trim stack trace to show better, reduced information to the user - Add --full-stacktrace to FIRRTL option to show full stack trace
2018-11-21Update description given that Chisel3 has been released (#948)edwardcwang
Now that Chisel3 has been released, you only need local Chisel to use the master branch in a project.
2018-11-21Bump sbt to 1.2.6; update dependencies (#941)Jim Lawson
* Bump sbt to 1.2.6; update dependencies * Add explanation for explicit junit library dependency
2018-11-20Make Vec cloneType keep directions of elements (#945)Jack Koenig
Fixes #893
2018-11-13Add Chisel logo to README (#935)Albert Magyar
2018-11-08Merge pull request #930 from albert-magyar/logoSchuyler Eldridge
- Add Chisel logo PNG and SVG to repo
2018-11-08Add SVG and PNG formatted Chisel logosAlbert Magyar
2018-11-05Convert to 2.1 .circleci/config.yml (#926)Jim Lawson
Use reusable executors and reusable commands.
2018-11-02Merge pull request #923 from freechipsproject/addstatustoreadmeSchuyler Eldridge
Add CircleCI status badge to README
2018-11-02Add CircleCI status badge to READMEJim Lawson
2018-11-02Fix Queue.io.count when entries=1 (#918)Andrew Waterman
Resolves #917
2018-11-02Circleci (#920)Jim Lawson
Be consistent with the use of /dev/null for sbt's stdin (force sbt to exit instead of bringing up a dialog). Enforce Jenkins' scalastyle limit of 40 warnings via CHECKSTYLE_LIMIT in environment. Force tests to run sequentially if -DminimalResources is set on the command line. Ensure we see valid scalastyle output. Make checkstyle dependent on one of the tests (so a style failure will fail the build only after tests pass).
2018-11-01Add BigInt / Int to Bool conversion (0.B, 1.B) (#913)Richard Lin
2018-10-29Turn off strong enum annotations (#916)Hasan Genc
* Turned off strong enum annotations because they weren't working with Vec indexes * Ignore annotation tests using ScalaTest's 'ignore', rather than by commenting them out
2018-10-29Fix LoadMemoryTransform for Instance Annotations (#914)Schuyler Eldridge
Quickfix for LoadMemoryTransform that gets this to work with Instance Annotations. The new Instance Annotations caused a corner case where a LoadMemoryAnnotation would be duplicated (via update/renaming) and the resulting annotation would differ from the original in only their originalMemoryNameOpt field. This corrects that by having the ChiselLoadMemoryAnnotation also emit the originalMemoryNameOpt field where it did not previously. First part of a fix for freechipsproject/firrtl#922. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-28Merge pull request #912 from seldridge/c911Schuyler Eldridge
Make BaseModule.name lazy
2018-10-25Check BaseModule.name for NullPointerExceptionSchuyler Eldridge
This wraps the evaluation of BaseModule.name in try/catch to look for a NullPointerException that may result from trying to evaluate desiredName before it's ready. This catches a test case of using a desiredName that depends on a later defined eager subinstance. h/t @jackkoenig Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>