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2018-08-22MixedVec: clarify dynamic indexing of heterogeneous elementsEdward Wang
2018-08-22Warn user that using Seq for hardware construction in Bundle is not supportedEdward Wang
2018-08-22Remove redundant := methodEdward Wang
2018-08-22MixedVec implementationEdward Wang
2018-08-22Minor tweaks to the style guide (#876)edwardcwang
2018-08-21Bump to Scala 2.12.6 and make it the default. (#858)Jim Lawson
2018-08-07BoringUtils / Synthesizable Cross Module References (#718)Schuyler Eldridge
This adds an annotator that provides a linkage to the FIRRTL WiringTransform. This enables synthesizable cross module references between one source and multiple sinks without changing IO (the WiringTransform bores through the hierarchy). Per WiringTransform, this will connect sources to their closest sinks (as determined by BFS) or fail if ownership is indeterminate. Make TesterDriver.execute work like Driver.execute: - annotations are included when running FIRRTL - custom transforms are run automatically Also, add a bore method to BoringUtils that allows you to do one source to multi-sink mapping in a single call. This adds a test that this is doing the same thing as the equivalent call via disjoint addSink/addSource. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-07-31Cleanup implicit conversions (#868)Jack Koenig
2018-07-31Ensure names work for bundles and literals. (#853)Jim Lawson
Fixes #852
2018-07-31Revert removal of bit extraction const prop for literals (#857)Jack Koenig
See https://github.com/freechipsproject/chisel3/issues/867 for future API discussion
2018-07-26Update latest release. (#863)Jim Lawson
2018-07-19Add support for Input() and Output() (available in Chisel2 since ↵Jim Lawson
ucb-bar/chisel2-deprecated#734) and test for same.
2018-07-11Update versions and links in README (#855)Jack Koenig
2018-07-10Fix use of read-only refs on rhs of connect in compatibility mode (#854)Jack Koenig
2018-07-09Bump recommended Verilator version to 3.922 (#851)Jim Lawson
2018-07-06Undeprecate log2Up and log2Down (#846)Jack Koenig
They should not be deprecated until zero-width wires actually work
2018-07-05Ignore eclipse temporariesRichard Lin
2018-07-04Change wording of internal failureRichard Lin
2018-07-04Fix strict namerRichard Lin
2018-07-04Remove forceName rom BlackBox/ExtModule, filter out forceName in UserModuleRichard Lin
2018-07-04Add test that UInt, SInt, and FP literals do not impact namingJack Koenig
2018-07-04Prefer litValue, eliminate litToBigIntducky
2018-07-04Change [public] Data.elementLitArg => [protected] Aggregate.litArgOfBitsducky
2018-07-04Style fixesducky
2018-07-04binding => topBinding so that partial Bundles work and undefined Bundle ↵ducky
members properly forward to DontCareBinding
2018-07-04properly fix undefined clock/reset issuesducky
2018-07-04Add BundleLiteralSpecRichard Lin
2018-07-04Comment out assertion test, fix ref generationRichard Lin
2018-07-04Add new test LitInsideOutsideTesterchick
This shows errors comparing literals
2018-07-04unbrokenducky
2018-07-04still brokenducky
2018-07-04brokenducky
2018-07-04delete debugging stuffducky
2018-07-04styleducky
2018-07-04Run-unique idsducky
2018-07-04lol=(Richard Lin
2018-07-04bundle literal mockup, but broken =(Richard Lin
2018-07-04refactoring of lit and ref implementationsRichard Lin
2018-07-04work on new style literal accessorsducky
2018-07-04Infrastructure for bundle literalsducky
2018-07-02Direct to FIRRTL (#829)Jack Koenig
Provide direct conversion from ChiselIR to FIRRTL. Provide Driver support for dumping ProtoBuf.
2018-06-29Catch returns from within when blocks and provide an error message (#842)Jack Koenig
Resolves #841
2018-06-29Add Emacs temporaries, backups to .gitignore (#837)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-06-25Correcting documentation errors in Arbiter.scala (#839)Brendan Sweeney
Documentation for example had parameters in wrong order, and was missing @param. Additionally, it was lacking a module wrapper. This has been corrected.
2018-06-20Programmatic Port Creation (#833)Jack Koenig
Add chisel3.experimental.IO for programmatic port creation in Raw and MultiIOModules. suggestName is required to name ports that cannot be named by reflection. Two ports cannot be given the same name.
2018-06-18Fixed UIntToOH(x, 1) invocation with x.width == 0 (#778)Wesley W. Terpstra
2018-06-01Literals set their ref so they no longer get named (#826)Jack Koenig
Fixes #763 Add tests for #763 and #472 This has a few implications * Constructing a literal no longer increments _T_ suffixes * Internally, wrapping a literal Bits in Node(...) will work * Literal Bools work in withReset/withClockAndReset
2018-05-31Suggest wrapping in Wire(_) or IO(_) in requireIsHardware (#827)Jack Koenig
2018-05-24Use Vec.apply instead of new Vec in VecInit.apply (#825)Jack Koenig
The Vec constructor invokes the gen argument for each element in the Vec. Since VecInit invokes cloneSupertype which touches every element of the input Seq, this was an n^2 operation. Vec.apply accepts its arguments by value so cloneSupertype is only called once. It then calls cloneType on that once for each element in the Vec, which is constant time reducing the overall complexity of VecInit to just n.
2018-05-24Remove extraneous traversal in cloneSupertype (#824)Jack Koenig
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