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AgeCommit message (Expand)Author
2022-05-27Make ExtModule port naming consistent with Module (#2548) (#2549)mergify[bot]
2022-05-24Support Vecs of empty Bundles (#2543) (#2545)mergify[bot]
2022-05-19Support := views to DontCare (#2536) (#2539)mergify[bot]
2022-05-19Update experimental-features.md (#2537) (#2538)mergify[bot]
2022-05-14Deprecate named arguments for methods moving to macros in 3.6 (#2530)Jack Koenig
2022-05-13Update mimaPreviousArtifacts to 3.5.3 (#2529)Jack Koenig
2022-05-12Update CONTRIBUTING.md for backport cleanup process (backport #2523) (#2524)mergify[bot]
2022-05-12Support separately elaborating definition and instance in ChiselStage (backpo...mergify[bot]
2022-04-26Fix spurious warning from Bundle plugin (#2506) (#2507)mergify[bot]
2022-04-25Fix error message for BlackBox without val io <: Record (#2504) (#2505)mergify[bot]
2022-04-25Fix warning injected into user code by @chiselName (#2500) (#2503)mergify[bot]
2022-04-20Generate a balanced tree with reduceTree (#2318) (#2499)mergify[bot]
2022-04-19Allow creating memories without an implicit clock (#2494) (#2495)mergify[bot]
2022-04-19verification: switch order of assert/assume and printf (#2484) (#2493)mergify[bot]
2022-04-18Fix small typos in doc comment (#2490) (#2492)mergify[bot]
2022-04-18Clarify example in Printable (#2454) (#2456)mergify[bot]
2022-04-15Enable Clock Invalidation (#2485) (#2487)mergify[bot]
2022-04-12Optimize memory use of naming prefixes (#2471) (#2480)mergify[bot]
2022-04-12Enhance views to [sometimes] support dynamic indexing and implement FlatIO (b...mergify[bot]
2022-04-05Micro-optimize Namespace.name (#2474) (#2475)mergify[bot]
2022-04-05Micro-optimize String building in _computeName (#2472) (#2473)mergify[bot]
2022-04-01Prevent FIRRTL bulk connects on BlackBox Bundles. (#2468) (#2469)mergify[bot]
2022-03-30Use var List instead of ListBuffer to save memory (#2465) (#2467)mergify[bot]
2022-03-25rm unused/deprecated BlackBoxResourceAnno import (#2458) (#2460)mergify[bot]
2022-03-15[docs] Add Cookbook section on aliased Bundle fields (#2444) (#2448)mergify[bot]
2022-03-10Emit FIRRTL bulkconnects whenever possible (#2381) (#2440)mergify[bot]
2022-03-09Support BlackBoxes in D/I (#2438) (#2442)mergify[bot]
2022-03-08Add scanLeftOr and scanRightOr utilies (#2407) (#2437)mergify[bot]
2022-03-07Tweaks to the Verilog-vs-Chisel Page (#2432) (#2433)mergify[bot]
2022-03-04Add SVG Version of Bundle Example Diagram (#2425) (#2431)mergify[bot]
2022-03-04Issue errors on out-of-range extracts when width is known (#2428) (#2429)mergify[bot]
2022-03-03Add Verilog-chisel side by side Reference Page to Docs (#2323) (#2426)mergify[bot]
2022-02-15Make TruthTable accept unknown input width (#2387) (#2417)mergify[bot]
2022-02-11Hierarchy API: make Mems lookupable (#2404) (#2410)mergify[bot]
2022-02-10Make Tuple2 Lookupable (#2372) (#2406)mergify[bot]
2022-02-08Overload getVerilogString to accept arguments (#2401) (#2402)mergify[bot]
2022-02-04Fix variable-name typo (#2397) (#2400)mergify[bot]
2022-02-04Fix bundle elements performance regression (#2396) (#2398)mergify[bot]
2022-02-03FillInterleaved documentation: swap order of elements in Seq example (#2393) ...mergify[bot]
2022-02-03Tweak Bundle._elementsImpl (#2390) (#2392)mergify[bot]
2022-02-03Tweak new mem port clock warnings (#2389) (#2391)mergify[bot]
2022-02-02Add Scala 2.13.8 to plugin cross-compilation (#2385) (#2386)mergify[bot]
2022-02-01Improve error reporting (backport #2376) (#2379)mergify[bot]
2022-02-01Optional clock param for memory ports (#2333) (#2382)mergify[bot]
2022-02-01Chisel plugin bundle elements handler (#2306) (#2380)mergify[bot]
2022-01-28Fix Decoder bug for constant 0 and DC (#2363) (#2371)mergify[bot]
2022-01-26Expand supported val modifiers for @public (#2365) (#2367)mergify[bot]
2022-01-20Fix Compatibility Module io wrapping (#2355) (#2358)mergify[bot]
2022-01-20Fix link to Naming Cookbook (#2356) (#2357)mergify[bot]
2022-01-19util: add GrayCode (#2353) (#2354)mergify[bot]
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