diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/chisel3/util/experimental/decode/decoder.scala | 6 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/util/BitSetSpec.scala | 29 |
2 files changed, 32 insertions, 3 deletions
diff --git a/src/main/scala/chisel3/util/experimental/decode/decoder.scala b/src/main/scala/chisel3/util/experimental/decode/decoder.scala index 067dd6f8..ce2da3c0 100644 --- a/src/main/scala/chisel3/util/experimental/decode/decoder.scala +++ b/src/main/scala/chisel3/util/experimental/decode/decoder.scala @@ -107,8 +107,10 @@ object decoder extends LazyLogging { { bitSets.zipWithIndex.flatMap { case (bs, i) => - bs.terms.map(bp => s"${bp.rawString}->${if (errorBit) "0"}${"0" * (bitSets.size - i - 1)}1${"0" * i}") - } ++ Seq(s"${if (errorBit) "1"}${"?" * bitSets.size}") + bs.terms.map(bp => + s"${bp.rawString}->${if (errorBit) "0" else ""}${"0" * (bitSets.size - i - 1)}1${"0" * i}" + ) + } ++ Seq(s"${if (errorBit) "1" ++ "0" * bitSets.size else "?" * bitSets.size}") }.mkString("\n") ) ) diff --git a/src/test/scala/chiselTests/util/BitSetSpec.scala b/src/test/scala/chiselTests/util/BitSetSpec.scala index dd66ba40..cf5f54cf 100644 --- a/src/test/scala/chiselTests/util/BitSetSpec.scala +++ b/src/test/scala/chiselTests/util/BitSetSpec.scala @@ -110,9 +110,36 @@ class BitSetSpec extends AnyFlatSpec with Matchers { "b11??????" ) ), - true + errorBit = true ) }) } + it should "be decoded with DontCare error" in { + import chisel3._ + import chisel3.util.experimental.decode.decoder + // [0 - 256] part into: [0 - 31], [32 - 47, 64 - 127], [192 - 255] + // "0011????" "10??????" is empty to error + chisel3.stage.ChiselStage.emitSystemVerilog(new Module { + val in = IO(Input(UInt(8.W))) + val out = IO(Output(UInt(4.W))) + out := decoder.bitset( + in, + Seq( + BitSet.fromString( + "b000?????" + ), + BitSet.fromString( + """b0010???? + |b01?????? + |""".stripMargin + ), + BitSet.fromString( + "b11??????" + ) + ), + errorBit = false + ) + }) + } } |