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-rw-r--r--src/test/scala/chiselTests/Assert.scala2
-rw-r--r--src/test/scala/chiselTests/BlackBox.scala32
-rw-r--r--src/test/scala/chiselTests/BundleWire.scala8
-rw-r--r--src/test/scala/chiselTests/ComplexAssign.scala10
-rw-r--r--src/test/scala/chiselTests/Decoder.scala8
-rw-r--r--src/test/scala/chiselTests/DeqIOSpec.scala11
-rw-r--r--src/test/scala/chiselTests/Direction.scala8
-rw-r--r--src/test/scala/chiselTests/EnableShiftRegister.scala10
-rw-r--r--src/test/scala/chiselTests/GCD.scala14
-rw-r--r--src/test/scala/chiselTests/LFSR16.scala8
-rw-r--r--src/test/scala/chiselTests/MemorySearch.scala12
-rw-r--r--src/test/scala/chiselTests/Module.scala22
-rw-r--r--src/test/scala/chiselTests/MulLookup.scala10
-rw-r--r--src/test/scala/chiselTests/OptionBundle.scala6
-rw-r--r--src/test/scala/chiselTests/Padding.scala10
-rw-r--r--src/test/scala/chiselTests/ParameterizedModule.scala8
-rw-r--r--src/test/scala/chiselTests/Risc.scala16
-rw-r--r--src/test/scala/chiselTests/SIntOps.scala36
-rw-r--r--src/test/scala/chiselTests/Stack.scala14
-rw-r--r--src/test/scala/chiselTests/Tbl.scala14
-rw-r--r--src/test/scala/chiselTests/UIntOps.scala50
-rw-r--r--src/test/scala/chiselTests/Vec.scala30
-rw-r--r--src/test/scala/chiselTests/VectorPacketIO.scala9
-rw-r--r--src/test/scala/chiselTests/VendingMachine.scala9
24 files changed, 165 insertions, 192 deletions
diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index 3fed2bd4..efc2e1e7 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -26,7 +26,7 @@ class SucceedingAssertTester() extends BasicTester {
}
class PipelinedResetModule extends Module {
- val io = new Bundle { }
+ val io = IO(new Bundle { })
val a = Reg(init = UInt(0xbeef))
val b = Reg(init = UInt(0xbeef))
assert(a === b)
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index fdc5970e..c1154883 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -10,25 +10,25 @@ import chisel3.testers.BasicTester
import chisel3.util._
class BlackBoxInverter extends BlackBox {
- val io = new Bundle() {
- val in = Bool(INPUT)
- val out = Bool(OUTPUT)
- }
+ val io = IO(new Bundle() {
+ val in = Input(Bool())
+ val out = Output(Bool())
+ })
}
class BlackBoxPassthrough extends BlackBox {
- val io = new Bundle() {
- val in = Bool(INPUT)
- val out = Bool(OUTPUT)
- }
+ val io = IO(new Bundle() {
+ val in = Input(Bool())
+ val out = Output(Bool())
+ })
}
class BlackBoxRegister extends BlackBox {
- val io = new Bundle() {
- val clock = Clock().asInput
- val in = Bool(INPUT)
- val out = Bool(OUTPUT)
- }
+ val io = IO(new Bundle() {
+ val clock = Input(Clock())
+ val in = Input(Bool())
+ val out = Output(Bool())
+ })
}
class BlackBoxTester extends BasicTester {
@@ -86,9 +86,9 @@ class BlackBoxWithClockTester extends BasicTester {
/*
// Must determine how to handle parameterized Verilog
class BlackBoxConstant(value: Int) extends BlackBox {
- val io = new Bundle() {
- val out = UInt(width=log2Up(value)).asOutput
- }
+ val io = IO(new Bundle() {
+ val out = Output(UInt(width=log2Up(value)))
+ })
override val name = s"#(WIDTH=${log2Up(value)},VALUE=$value) "
}
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index e5e9fb1a..029407dd 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -12,10 +12,10 @@ class Coord extends Bundle {
}
class BundleWire(n: Int) extends Module {
- val io = new Bundle {
- val in = (new Coord).asInput
- val outs = Vec(n, new Coord).asOutput
- }
+ val io = IO(new Bundle {
+ val in = Input(new Coord)
+ val outs = Output(Vec(n, new Coord))
+ })
val coords = Wire(Vec(n, new Coord))
for (i <- 0 until n) {
coords(i) := io.in
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index 304fbcf5..e5d1fbea 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -15,11 +15,11 @@ class Complex[T <: Data](val re: T, val im: T) extends Bundle {
}
class ComplexAssign(w: Int) extends Module {
- val io = new Bundle {
- val e = new Bool(INPUT)
- val in = new Complex(UInt(width = w), UInt(width = w)).asInput
- val out = new Complex(UInt(width = w), UInt(width = w)).asOutput
- }
+ val io = IO(new Bundle {
+ val e = Input(Bool())
+ val in = Input(new Complex(UInt(width = w), UInt(width = w)))
+ val out = Output(new Complex(UInt(width = w), UInt(width = w)))
+ })
when (io.e) {
val tmp = Wire(new Complex(UInt(width = w), UInt(width = w)))
tmp := io.in
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index 5586561b..4a872245 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -11,10 +11,10 @@ import chisel3.testers.BasicTester
import chisel3.util._
class Decoder(bitpats: List[String]) extends Module {
- val io = new Bundle {
- val inst = UInt(INPUT, 32)
- val matched = Bool(OUTPUT)
- }
+ val io = IO(new Bundle {
+ val inst = Input(UInt(32))
+ val matched = Output(Bool())
+ })
io.matched := Vec(bitpats.map(BitPat(_) === io.inst)).reduce(_||_)
}
diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
index 09891647..770d2e0e 100644
--- a/src/test/scala/chiselTests/DeqIOSpec.scala
+++ b/src/test/scala/chiselTests/DeqIOSpec.scala
@@ -16,17 +16,17 @@ class UsesDeqIOInfo extends Bundle {
}
class UsesDeqIO extends Module {
- val io = new Bundle {
- val in = new DeqIO(new UsesDeqIOInfo)
- val out = new EnqIO(new UsesDeqIOInfo)
- }
+ val io = IO(new Bundle {
+ val in = DeqIO(new UsesDeqIOInfo)
+ val out = EnqIO(new UsesDeqIOInfo)
+ })
}
class DeqIOSpec extends ChiselFlatSpec {
runTester {
new BasicTester {
val dut = new UsesDeqIO
-
+/*
"DeqIO" should "set the direction of it's parameter to INPUT" in {
assert(dut.io.in.bits.info_data.dir === INPUT)
}
@@ -56,6 +56,7 @@ class DeqIOSpec extends ChiselFlatSpec {
assert(dut.io.out.ready.dir == out_clone.ready.dir)
assert(dut.io.out.valid.dir == out_clone.valid.dir)
}
+ */
}
}
}
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 8b84f844..682103f7 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -8,10 +8,10 @@ import org.scalatest.prop._
import chisel3.testers.BasicTester
class DirectionHaver extends Module {
- val io = new Bundle {
- val in = UInt(INPUT, 32)
- val out = UInt(OUTPUT, 32)
- }
+ val io = IO(new Bundle {
+ val in = Input(UInt(32))
+ val out = Output(UInt(32))
+ })
}
class GoodDirection extends DirectionHaver {
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 7db20fc1..26af944f 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -5,11 +5,11 @@ import chisel3._
import chisel3.testers.BasicTester
class EnableShiftRegister extends Module {
- val io = new Bundle {
- val in = UInt(INPUT, 4)
- val shift = Bool(INPUT)
- val out = UInt(OUTPUT, 4)
- }
+ val io = IO(new Bundle {
+ val in = Input(UInt(4))
+ val shift = Input(Bool())
+ val out = Output(UInt(4))
+ })
val r0 = Reg(init = UInt(0, 4))
val r1 = Reg(init = UInt(0, 4))
val r2 = Reg(init = UInt(0, 4))
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index 60a70cc8..a8b907af 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -8,13 +8,13 @@ import org.scalatest._
import org.scalatest.prop._
class GCD extends Module {
- val io = new Bundle {
- val a = UInt(INPUT, 32)
- val b = UInt(INPUT, 32)
- val e = Bool(INPUT)
- val z = UInt(OUTPUT, 32)
- val v = Bool(OUTPUT)
- }
+ val io = IO(new Bundle {
+ val a = Input(UInt(32))
+ val b = Input(UInt(32))
+ val e = Input(Bool())
+ val z = Output(UInt(32))
+ val v = Output(Bool())
+ })
val x = Reg(UInt(width = 32))
val y = Reg(UInt(width = 32))
when (x > y) { x := x -% y }
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index a1699441..2d5e7f3e 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -7,10 +7,10 @@ import chisel3.testers.BasicTester
import chisel3.util._
class LFSR16 extends Module {
- val io = new Bundle {
- val inc = Bool(INPUT)
- val out = UInt(OUTPUT, 16)
- }
+ val io = IO(new Bundle {
+ val inc = Input(Bool())
+ val out = Output(UInt(16))
+ })
val res = Reg(init = UInt(1, 16))
when (io.inc) {
val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1))
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index 679b894c..770be326 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -6,12 +6,12 @@ import chisel3._
import chisel3.testers.BasicTester
class MemorySearch extends Module {
- val io = new Bundle {
- val target = UInt(INPUT, 4)
- val en = Bool(INPUT)
- val done = Bool(OUTPUT)
- val address = UInt(OUTPUT, 3)
- }
+ val io = IO(new Bundle {
+ val target = Input(UInt(4))
+ val en = Input(Bool())
+ val done = Output(Bool())
+ val address = Output(UInt(3))
+ })
val vals = Array(0, 4, 15, 14, 2, 5, 13)
val index = Reg(init = UInt(0, width = 3))
val elts = Vec(vals.map(UInt(_,4)))
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 23788b72..7c0bc40e 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -5,20 +5,20 @@ package chiselTests
import chisel3._
class SimpleIO extends Bundle {
- val in = UInt(INPUT, 32)
- val out = UInt(OUTPUT, 32)
+ val in = Input(UInt(32))
+ val out = Output(UInt(32))
}
class PlusOne extends Module {
- val io = new SimpleIO
+ val io = IO(new SimpleIO)
io.out := io.in + UInt(1)
}
class ModuleVec(val n: Int) extends Module {
- val io = new Bundle {
- val ins = Vec(n, UInt(INPUT, 32))
- val outs = Vec(n, UInt(OUTPUT, 32))
- }
+ val io = IO(new Bundle {
+ val ins = Input(Vec(n, UInt(32)))
+ val outs = Output(Vec(n, UInt(32)))
+ })
val pluses = Vec.fill(n){ Module(new PlusOne).io }
for (i <- 0 until n) {
pluses(i).in := io.ins(i)
@@ -40,8 +40,8 @@ class ModuleVecTester(c: ModuleVec) extends Tester(c) {
*/
class ModuleWire extends Module {
- val io = new SimpleIO
- val inc = Wire(Module(new PlusOne).io)
+ val io = IO(new SimpleIO)
+ val inc = Wire(Module(new PlusOne).io.newType)
inc.in := io.in
io.out := inc.out
}
@@ -58,10 +58,10 @@ class ModuleWireTester(c: ModuleWire) extends Tester(c) {
*/
class ModuleWhen extends Module {
- val io = new Bundle {
+ val io = IO(new Bundle {
val s = new SimpleIO
val en = Bool()
- }
+ })
when(io.en) {
val inc = Module(new PlusOne).io
inc.in := io.s.in
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index 831e323f..b22b2820 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -8,11 +8,11 @@ import org.scalatest.prop._
import chisel3.testers.BasicTester
class MulLookup(val w: Int) extends Module {
- val io = new Bundle {
- val x = UInt(INPUT, w)
- val y = UInt(INPUT, w)
- val z = UInt(OUTPUT, 2 * w)
- }
+ val io = IO(new Bundle {
+ val x = Input(UInt(w))
+ val y = Input(UInt(w))
+ val z = Output(UInt(2 * w))
+ })
val tbl = Vec(
for {
i <- 0 until 1 << w
diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala
index fa691b43..8e4c7579 100644
--- a/src/test/scala/chiselTests/OptionBundle.scala
+++ b/src/test/scala/chiselTests/OptionBundle.scala
@@ -8,15 +8,15 @@ import chisel3.testers.BasicTester
class OptionBundle(hasIn: Boolean) extends Bundle {
val in = if (hasIn) {
- Some(Bool(INPUT))
+ Some(Input(Bool()))
} else {
None
}
- val out = Bool(OUTPUT)
+ val out = Output(Bool())
}
class OptionBundleModule(hasIn: Boolean) extends Module {
- val io = new OptionBundle(hasIn)
+ val io = IO(new OptionBundle(hasIn))
if (hasIn) {
io.out := io.in.get
} else {
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index 3fb0f955..6c92e87b 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -5,11 +5,11 @@ package chiselTests
import chisel3._
class Padder extends Module {
- val io = new Bundle {
- val a = Bits(INPUT, 4)
- val asp = SInt(OUTPUT, 8)
- val aup = UInt(OUTPUT, 8)
- }
+ val io = IO(new Bundle {
+ val a = Input(UInt(4))
+ val asp = Output(SInt(8))
+ val aup = Output(UInt(8))
+ })
io.asp := io.a.asSInt
io.aup := io.a.asUInt
}
diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala
index 4859759e..14b21631 100644
--- a/src/test/scala/chiselTests/ParameterizedModule.scala
+++ b/src/test/scala/chiselTests/ParameterizedModule.scala
@@ -7,10 +7,10 @@ import chisel3._
import chisel3.testers.BasicTester
class ParameterizedModule(invert: Boolean) extends Module {
- val io = new Bundle {
- val in = new Bool(INPUT)
- val out = new Bool(OUTPUT)
- }
+ val io = IO(new Bundle {
+ val in = Input(Bool())
+ val out = Output(Bool())
+ })
if (invert) {
io.out := !io.in
} else {
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index f5e61115..fafec95a 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -6,14 +6,14 @@ import chisel3._
import chisel3.util._
class Risc extends Module {
- val io = new Bundle {
- val isWr = Bool(INPUT)
- val wrAddr = UInt(INPUT, 8)
- val wrData = Bits(INPUT, 32)
- val boot = Bool(INPUT)
- val valid = Bool(OUTPUT)
- val out = Bits(OUTPUT, 32)
- }
+ val io = IO(new Bundle {
+ val isWr = Input(Bool())
+ val wrAddr = Input(UInt(8))
+ val wrData = Input(Bits(32))
+ val boot = Input(Bool())
+ val valid = Output(Bool())
+ val out = Output(Bits(32))
+ })
val memSize = 256
val file = Mem(memSize, Bits(width = 32))
val code = Mem(memSize, Bits(width = 32))
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index 6cd013f1..a98edf9b 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -6,24 +6,24 @@ import chisel3._
import chisel3.testers.BasicTester
class SIntOps extends Module {
- val io = new Bundle {
- val a = SInt(INPUT, 16)
- val b = SInt(INPUT, 16)
- val addout = SInt(OUTPUT, 16)
- val subout = SInt(OUTPUT, 16)
- val timesout = SInt(OUTPUT, 16)
- val divout = SInt(OUTPUT, 16)
- val modout = SInt(OUTPUT, 16)
- val lshiftout = SInt(OUTPUT, 16)
- val rshiftout = SInt(OUTPUT, 16)
- val lessout = Bool(OUTPUT)
- val greatout = Bool(OUTPUT)
- val eqout = Bool(OUTPUT)
- val noteqout = Bool(OUTPUT)
- val lesseqout = Bool(OUTPUT)
- val greateqout = Bool(OUTPUT)
- val negout = SInt(OUTPUT, 16)
- }
+ val io = IO(new Bundle {
+ val a = Input(SInt(16))
+ val b = Input(SInt(16))
+ val addout = Output(SInt(16))
+ val subout = Output(SInt(16))
+ val timesout = Output(SInt(16))
+ val divout = Output(SInt(16))
+ val modout = Output(SInt(16))
+ val lshiftout = Output(SInt(16))
+ val rshiftout = Output(SInt(16))
+ val lessout = Output(Bool())
+ val greatout = Output(Bool())
+ val eqout = Output(Bool())
+ val noteqout = Output(Bool())
+ val lesseqout = Output(Bool())
+ val greateqout = Output(Bool())
+ val negout = Output(SInt(16))
+ })
val a = io.a
val b = io.b
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index cbd9f3e3..683c5224 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -8,13 +8,13 @@ import chisel3._
import chisel3.util._
class ChiselStack(val depth: Int) extends Module {
- val io = new Bundle {
- val push = Bool(INPUT)
- val pop = Bool(INPUT)
- val en = Bool(INPUT)
- val dataIn = UInt(INPUT, 32)
- val dataOut = UInt(OUTPUT, 32)
- }
+ val io = IO(new Bundle {
+ val push = Input(Bool())
+ val pop = Input(Bool())
+ val en = Input(Bool())
+ val dataIn = Input(UInt(32))
+ val dataOut = Output(UInt(32))
+ })
val stack_mem = Mem(depth, UInt(width = 32))
val sp = Reg(init = UInt(0, width = log2Up(depth + 1)))
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index d84cd85e..6ebe0875 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -10,13 +10,13 @@ import chisel3.testers.BasicTester
import chisel3.util._
class Tbl(w: Int, n: Int) extends Module {
- val io = new Bundle {
- val wi = UInt(INPUT, log2Up(n))
- val ri = UInt(INPUT, log2Up(n))
- val we = Bool(INPUT)
- val d = UInt(INPUT, w)
- val o = UInt(OUTPUT, w)
- }
+ val io = IO(new Bundle {
+ val wi = Input(UInt(log2Up(n)))
+ val ri = Input(UInt(log2Up(n)))
+ val we = Input(Bool())
+ val d = Input(UInt(w))
+ val o = Output(UInt(w))
+ })
val m = Mem(n, UInt(width = w))
io.o := m(io.ri)
when (io.we) {
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index c5069fc4..ca83ee1d 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -7,23 +7,23 @@ import org.scalatest._
import chisel3.testers.BasicTester
class UIntOps extends Module {
- val io = new Bundle {
- val a = UInt(INPUT, 16)
- val b = UInt(INPUT, 16)
- val addout = UInt(OUTPUT, 16)
- val subout = UInt(OUTPUT, 16)
- val timesout = UInt(OUTPUT, 16)
- val divout = UInt(OUTPUT, 16)
- val modout = UInt(OUTPUT, 16)
- val lshiftout = UInt(OUTPUT, 16)
- val rshiftout = UInt(OUTPUT, 16)
- val lessout = Bool(OUTPUT)
- val greatout = Bool(OUTPUT)
- val eqout = Bool(OUTPUT)
- val noteqout = Bool(OUTPUT)
- val lesseqout = Bool(OUTPUT)
- val greateqout = Bool(OUTPUT)
- }
+ val io = IO(new Bundle {
+ val a = Input(UInt(16))
+ val b = Input(UInt(16))
+ val addout = Output(UInt(16))
+ val subout = Output(UInt(16))
+ val timesout = Output(UInt(16))
+ val divout = Output(UInt(16))
+ val modout = Output(UInt(16))
+ val lshiftout = Output(UInt(16))
+ val rshiftout = Output(UInt(16))
+ val lessout = Output(Bool())
+ val greatout = Output(Bool())
+ val eqout = Output(Bool())
+ val noteqout = Output(Bool())
+ val lesseqout = Output(Bool())
+ val greateqout = Output(Bool())
+ })
val a = io.a
val b = io.b
@@ -77,18 +77,18 @@ class UIntOpsTester(c: UIntOps) extends Tester(c) {
*/
class GoodBoolConversion extends Module {
- val io = new Bundle {
- val u = UInt(1, width = 1).asInput
- val b = Bool(OUTPUT)
- }
+ val io = IO(new Bundle {
+ val u = Input(UInt(1))
+ val b = Output(Bool())
+ })
io.b := io.u.toBool
}
class BadBoolConversion extends Module {
- val io = new Bundle {
- val u = UInt(1, width = 5).asInput
- val b = Bool(OUTPUT)
- }
+ val io = IO(new Bundle {
+ val u = Input(UInt(width = 5))
+ val b = Output(Bool())
+ })
io.b := io.u.toBool
}
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 7dd80a13..b90c1f09 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -43,32 +43,6 @@ class ShiftRegisterTester(n: Int) extends BasicTester {
}
}
-class FunBundle extends Bundle {
- val stuff = UInt(width = 10)
-}
-
-class ZeroModule extends Module {
- val io = new Bundle {
- val mem = UInt(width = 10)
- val interrupts = Vec(2, Bool()).asInput
- val mmio_axi = Vec(0, new FunBundle)
- val mmio_ahb = Vec(0, new FunBundle).flip
- }
-
- io.mmio_axi <> io.mmio_ahb
-
- io.mem := UInt(0)
- when (io.interrupts(0)) { io.mem := UInt(1) }
- when (io.interrupts(1)) { io.mem := UInt(2) }
-}
-
-class ZeroTester extends BasicTester {
- val foo = Module(new ZeroModule)
- foo.io.interrupts := Vec.tabulate(2) { _ => Bool(true) }
- assert (foo.io.mem === UInt(2))
- stop()
-}
-
class VecSpec extends ChiselPropSpec {
property("Vecs should be assignable") {
forAll(safeUIntN(8)) { case(w: Int, v: List[Int]) =>
@@ -83,8 +57,4 @@ class VecSpec extends ChiselPropSpec {
property("Regs of vecs should be usable as shift registers") {
forAll(smallPosInts) { (n: Int) => assertTesterPasses{ new ShiftRegisterTester(n) } }
}
-
- property("Dual empty Vectors") {
- assertTesterPasses{ new ZeroTester }
- }
}
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 07779faa..081990ad 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -28,8 +28,8 @@ class Packet extends Bundle {
* The problem does not occur if the Vec is taken out
*/
class VectorPacketIO(n: Int) extends Bundle {
- val ins = Vec(n, new DeqIO(new Packet()))
- val outs = Vec(n, new EnqIO(new Packet()))
+ val ins = Vec(n, DeqIO(new Packet()))
+ val outs = Vec(n, EnqIO(new Packet()))
}
/**
@@ -38,10 +38,11 @@ class VectorPacketIO(n: Int) extends Bundle {
*/
class BrokenVectorPacketModule extends Module {
val n = 4
- val io = new VectorPacketIO(n)
+ val io = IO(new VectorPacketIO(n))
/* the following method of initializing the circuit may change in the future */
- io.outs.foreach(_.init())
+ io.ins.foreach(_.noenq())
+ io.outs.foreach(_.nodeq())
}
class VectorPacketIOUnitTester extends BasicTester {
diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala
index f03cb881..00b1e7de 100644
--- a/src/test/scala/chiselTests/VendingMachine.scala
+++ b/src/test/scala/chiselTests/VendingMachine.scala
@@ -6,10 +6,11 @@ import chisel3._
import chisel3.util._
class VendingMachine extends Module {
- val io = new Bundle {
- val nickel = Bool(dir = INPUT)
- val dime = Bool(dir = INPUT)
- val valid = Bool(dir = OUTPUT) }
+ val io = IO(new Bundle {
+ val nickel = Input(Bool())
+ val dime = Input(Bool())
+ val valid = Output(Bool())
+ })
val c = UInt(5, width = 3)
val sIdle :: s5 :: s10 :: s15 :: sOk :: Nil = Enum(UInt(), 5)
val state = Reg(init = sIdle)
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-30 19:13:57 +0000