diff options
Diffstat (limited to 'src/test')
40 files changed, 268 insertions, 268 deletions
diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala index efc2e1e7..475e18f7 100644 --- a/src/test/scala/chiselTests/Assert.scala +++ b/src/test/scala/chiselTests/Assert.scala @@ -8,7 +8,7 @@ import chisel3.testers.BasicTester import chisel3.util._ class FailingAssertTester() extends BasicTester { - assert(Bool(false)) + assert(false.B) // Wait to come out of reset val (_, done) = Counter(!reset, 4) when (done) { @@ -17,7 +17,7 @@ class FailingAssertTester() extends BasicTester { } class SucceedingAssertTester() extends BasicTester { - assert(Bool(true)) + assert(true.B) // Wait to come out of reset val (_, done) = Counter(!reset, 4) when (done) { @@ -27,8 +27,8 @@ class SucceedingAssertTester() extends BasicTester { class PipelinedResetModule extends Module { val io = IO(new Bundle { }) - val a = Reg(init = UInt(0xbeef)) - val b = Reg(init = UInt(0xbeef)) + val a = Reg(init = 0xbeef.U) + val b = Reg(init = 0xbeef.U) assert(a === b) } diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala index f5872adb..df23f0a2 100644 --- a/src/test/scala/chiselTests/BetterNamingTests.scala +++ b/src/test/scala/chiselTests/BetterNamingTests.scala @@ -9,14 +9,14 @@ import chisel3.util._ // Defined outside of the class so we don't get $ in name class Other(w: Int) extends Module { val io = new Bundle { - val a = UInt(width = w) + val a = UInt(w.W) } } class PerNameIndexing(count: Int) extends Module { val io = new Bundle { } val wires = Seq.tabulate(count) { i => Module(new Other(i)) } - val queues = Seq.tabulate(count) { i => Module(new Queue(UInt(width = i), 16)) } + val queues = Seq.tabulate(count) { i => Module(new Queue(UInt(i.W), 16)) } } // Note this only checks Iterable[Chisel.Data] which excludes Maps diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala index d8821134..8b4cf157 100644 --- a/src/test/scala/chiselTests/BlackBox.scala +++ b/src/test/scala/chiselTests/BlackBox.scala @@ -37,11 +37,11 @@ class BlackBoxTester extends BasicTester { val blackBoxPos = Module(new BlackBoxInverter) val blackBoxNeg = Module(new BlackBoxInverter) - blackBoxPos.io.in := UInt(1) - blackBoxNeg.io.in := UInt(0) + blackBoxPos.io.in := 1.U + blackBoxNeg.io.in := 0.U - assert(blackBoxNeg.io.out === UInt(1)) - assert(blackBoxPos.io.out === UInt(0)) + assert(blackBoxNeg.io.out === 1.U) + assert(blackBoxPos.io.out === 0.U) stop() } @@ -56,15 +56,15 @@ class MultiBlackBoxTester extends BasicTester { val blackBoxPassPos = Module(new BlackBoxPassthrough) val blackBoxPassNeg = Module(new BlackBoxPassthrough) - blackBoxInvPos.io.in := UInt(1) - blackBoxInvNeg.io.in := UInt(0) - blackBoxPassPos.io.in := UInt(1) - blackBoxPassNeg.io.in := UInt(0) + blackBoxInvPos.io.in := 1.U + blackBoxInvNeg.io.in := 0.U + blackBoxPassPos.io.in := 1.U + blackBoxPassNeg.io.in := 0.U - assert(blackBoxInvNeg.io.out === UInt(1)) - assert(blackBoxInvPos.io.out === UInt(0)) - assert(blackBoxPassNeg.io.out === UInt(0)) - assert(blackBoxPassPos.io.out === UInt(1)) + assert(blackBoxInvNeg.io.out === 1.U) + assert(blackBoxInvPos.io.out === 0.U) + assert(blackBoxPassNeg.io.out === 0.U) + assert(blackBoxPassPos.io.out === 1.U) stop() } @@ -72,14 +72,14 @@ class BlackBoxWithClockTester extends BasicTester { val blackBox = Module(new BlackBoxRegister) val model = Reg(Bool()) - val (cycles, end) = Counter(Bool(true), 15) + val (cycles, end) = Counter(true.B, 15) val impetus = cycles(0) blackBox.io.clock := clock blackBox.io.in := impetus model := impetus - when(cycles > UInt(0)) { + when(cycles > 0.U) { assert(blackBox.io.out === model) } when(end) { stop() } @@ -121,16 +121,16 @@ class BlackBoxWithParamsTester extends BasicTester { val blackBoxTypeParamBit = Module(new BlackBoxTypeParam(1, "bit")) val blackBoxTypeParamWord = Module(new BlackBoxTypeParam(32, "bit [31:0]")) - val (cycles, end) = Counter(Bool(true), 4) + val (cycles, end) = Counter(true.B, 4) - assert(blackBoxOne.io.out === UInt(1)) - assert(blackBoxFour.io.out === UInt(4)) - assert(blackBoxStringParamOne.io.out === UInt(1)) - assert(blackBoxStringParamTwo.io.out === UInt(2)) - assert(blackBoxRealParamOne.io.out === UInt(0x3ff0000000000000L)) - assert(blackBoxRealParamNeg.io.out === UInt(BigInt("bff0000000000000", 16))) - assert(blackBoxTypeParamBit.io.out === UInt(1)) - assert(blackBoxTypeParamWord.io.out === UInt("hdeadbeef", 32)) + assert(blackBoxOne.io.out === 1.U) + assert(blackBoxFour.io.out === 4.U) + assert(blackBoxStringParamOne.io.out === 1.U) + assert(blackBoxStringParamTwo.io.out === 2.U) + assert(blackBoxRealParamOne.io.out === 0x3ff0000000000000L.U) + assert(blackBoxRealParamNeg.io.out === BigInt("bff0000000000000", 16).U) + assert(blackBoxTypeParamBit.io.out === 1.U) + assert(blackBoxTypeParamWord.io.out === "hdeadbeef".U(32.W)) when(end) { stop() } } diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala index 5b38ff6e..0faab9d0 100644 --- a/src/test/scala/chiselTests/BundleWire.scala +++ b/src/test/scala/chiselTests/BundleWire.scala @@ -8,8 +8,8 @@ import chisel3.testers.BasicTester //import chisel3.core.ExplicitCompileOptions.Strict class Coord extends Bundle { - val x = UInt.width( 32) - val y = UInt.width( 32) + val x = UInt(32.W) + val y = UInt(32.W) } class BundleWire(n: Int) extends Module { @@ -26,12 +26,12 @@ class BundleWire(n: Int) extends Module { class BundleToUnitTester extends BasicTester { val bundle1 = Wire(new Bundle { - val a = UInt(width = 4) - val b = UInt(width = 4) + val a = UInt(4.W) + val b = UInt(4.W) }) val bundle2 = Wire(new Bundle { - val a = UInt(width = 2) - val b = UInt(width = 6) + val a = UInt(2.W) + val b = UInt(6.W) }) // 0b00011011 split as 0001 1011 and as 00 011011 @@ -47,11 +47,11 @@ class BundleToUnitTester extends BasicTester { class BundleWireTester(n: Int, x: Int, y: Int) extends BasicTester { val dut = Module(new BundleWire(n)) - dut.io.in.x := UInt(x) - dut.io.in.y := UInt(y) + dut.io.in.x := x.asUInt + dut.io.in.y := y.asUInt for (elt <- dut.io.outs) { - assert(elt.x === UInt(x)) - assert(elt.y === UInt(y)) + assert(elt.x === x.asUInt) + assert(elt.y === y.asUInt) } stop() } diff --git a/src/test/scala/chiselTests/Clock.scala b/src/test/scala/chiselTests/Clock.scala index 79dd2de4..78d60ed2 100644 --- a/src/test/scala/chiselTests/Clock.scala +++ b/src/test/scala/chiselTests/Clock.scala @@ -10,7 +10,7 @@ import chisel3.testers.BasicTester import chisel3.util._ class ClockAsUIntTester extends BasicTester { - assert(Bool(true).asClock.asUInt === UInt(1)) + assert(true.B.asClock.asUInt === 1.U) stop() } diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala index 57ceff3f..cc0a966c 100644 --- a/src/test/scala/chiselTests/CompileOptionsTest.scala +++ b/src/test/scala/chiselTests/CompileOptionsTest.scala @@ -27,12 +27,12 @@ class CompileOptionsSpec extends ChiselFlatSpec { } class SmallBundle extends Bundle { - val f1 = UInt(width = 4) - val f2 = UInt(width = 5) + val f1 = UInt(4.W) + val f2 = UInt(5.W) override def cloneType: this.type = (new SmallBundle).asInstanceOf[this.type] } class BigBundle extends SmallBundle { - val f3 = UInt(width = 6) + val f3 = UInt(6.W) override def cloneType: this.type = (new BigBundle).asInstanceOf[this.type] } @@ -73,7 +73,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { val in = Input(new SmallBundle) val out = Output(new BigBundle) }) - val badReg = Reg(UInt(7, width=4)) + val badReg = Reg(7.U(4.W)) } elaborate { new CreateRegFromBoundTypeModule() } } @@ -87,7 +87,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { val in = Input(new SmallBundle) val out = Output(new BigBundle) }) - val badReg = Reg(UInt(7, width=4)) + val badReg = Reg(7.U(4.W)) } elaborate { new CreateRegFromBoundTypeModule() } } @@ -97,7 +97,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { class RequireIOWrapModule extends Module { val io = IO(new Bundle { - val in = UInt(width = 32).asInput + val in = UInt(32.W).asInput val out = Bool().asOutput }) io.out := io.in(1) @@ -110,7 +110,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { class RequireIOWrapModule extends Module { val io = new Bundle { - val in = UInt(width = 32).asInput + val in = UInt(32.W).asInput val out = Bool().asOutput } io.out := io.in(1) @@ -124,7 +124,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { class RequireIOWrapModule extends Module { val io = new Bundle { - val in = UInt(width = 32).asInput + val in = UInt(32.W).asInput val out = Bool().asOutput } io.out := io.in(1) @@ -141,8 +141,8 @@ class CompileOptionsSpec extends ChiselFlatSpec { class SimpleModule extends Module { val io = IO(new Bundle { - val in = Input(UInt(width = 3)) - val out = Output(UInt(width = 4)) + val in = Input(UInt(3.W)) + val out = Output(UInt(4.W)) }) } class SwappedConnectionModule extends SimpleModule { @@ -158,8 +158,8 @@ class CompileOptionsSpec extends ChiselFlatSpec { class SimpleModule extends Module { val io = IO(new Bundle { - val in = Input(UInt(width = 3)) - val out = Output(UInt(width = 4)) + val in = Input(UInt(3.W)) + val out = Output(UInt(4.W)) }) } class SwappedConnectionModule extends SimpleModule { @@ -177,15 +177,15 @@ class CompileOptionsSpec extends ChiselFlatSpec { class SimpleModule extends Module { val io = IO(new Bundle { - val in = Input(UInt(width = 3)) - val out = Output(UInt(width = 4)) + val in = Input(UInt(3.W)) + val out = Output(UInt(4.W)) }) - val noDir = Wire(UInt(width = 3)) + val noDir = Wire(UInt(3.W)) } class DirectionLessConnectionModule extends SimpleModule { - val a = UInt(0, width = 3) - val b = Wire(UInt(width = 3)) + val a = 0.U(3.W) + val b = Wire(UInt(3.W)) val child = Module(new SimpleModule) b := child.noDir } @@ -198,15 +198,15 @@ class CompileOptionsSpec extends ChiselFlatSpec { class SimpleModule extends Module { val io = IO(new Bundle { - val in = Input(UInt(width = 3)) - val out = Output(UInt(width = 4)) + val in = Input(UInt(3.W)) + val out = Output(UInt(4.W)) }) - val noDir = Wire(UInt(width = 3)) + val noDir = Wire(UInt(3.W)) } class DirectionLessConnectionModule extends SimpleModule { - val a = UInt(0, width = 3) - val b = Wire(UInt(width = 3)) + val a = 0.U(3.W) + val b = Wire(UInt(3.W)) val child = Module(new SimpleModule) b := child.noDir } @@ -217,7 +217,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { implicit val strictWithoutIOWrap = StrictWithoutIOWrap class RequireIOWrapModule extends StrictModule { val io = IO(new Bundle { - val in = UInt(width = 32).asInput + val in = UInt(32.W).asInput val out = Bool().asOutput }) io.out := io.in(1) @@ -231,7 +231,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { implicit val strictWithoutIOWrap = StrictWithoutIOWrap class RequireIOWrapModule extends NotStrictModule { val io = new Bundle { - val in = UInt(width = 32).asInput + val in = UInt(32.W).asInput val out = Bool().asOutput } io.out := io.in(1) @@ -246,7 +246,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { implicit val strictWithoutIOWrap = StrictWithoutIOWrap class RequireIOWrapModule extends StrictModule { val io = new Bundle { - val in = UInt(width = 32).asInput + val in = UInt(32.W).asInput val out = Bool().asOutput } io.out := io.in(1) @@ -274,7 +274,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { } class NotIOWrapModule extends Module()(StrictNotIOWrap.CompileOptions) { val io = new Bundle { - val in = UInt(width = 32).asInput + val in = UInt(32.W).asInput val out = Bool().asOutput } } diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala index c5a23f82..f7484501 100644 --- a/src/test/scala/chiselTests/ComplexAssign.scala +++ b/src/test/scala/chiselTests/ComplexAssign.scala @@ -17,28 +17,28 @@ class Complex[T <: Data](val re: T, val im: T) extends Bundle { class ComplexAssign(w: Int) extends Module { val io = IO(new Bundle { val e = Input(Bool()) - val in = Input(new Complex(UInt.width(w), UInt.width(w))) - val out = Output(new Complex(UInt.width(w), UInt.width(w))) + val in = Input(new Complex(UInt(w.W), UInt(w.W))) + val out = Output(new Complex(UInt(w.W), UInt(w.W))) }) when (io.e) { - val tmp = Wire(new Complex(UInt.width(w), UInt.width(w))) + val tmp = Wire(new Complex(UInt(w.W), UInt(w.W))) tmp := io.in io.out.re := tmp.re io.out.im := tmp.im } .otherwise { - io.out.re := UInt(0) - io.out.im := UInt(0) + io.out.re := 0.U + io.out.im := 0.U } } class ComplexAssignTester(enList: List[Boolean], re: Int, im: Int) extends BasicTester { - val (cnt, wrap) = Counter(Bool(true), enList.size) + val (cnt, wrap) = Counter(true.B, enList.size) val dut = Module(new ComplexAssign(32)) - dut.io.in.re := UInt(re) - dut.io.in.im := UInt(im) + dut.io.in.re := re.asUInt + dut.io.in.im := im.asUInt dut.io.e := Vec(enList.map(Bool(_)))(cnt) - val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, UInt(0)) - val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, UInt(0)) + val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, 0.U) + val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, 0.U) assert(re_correct && im_correct) when(wrap) { stop() diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala index 69d8a44a..cccd8c0e 100644 --- a/src/test/scala/chiselTests/Counter.scala +++ b/src/test/scala/chiselTests/Counter.scala @@ -11,18 +11,18 @@ import chisel3.util._ class CountTester(max: Int) extends BasicTester { val cnt = Counter(max) - when(Bool(true)) { cnt.inc() } + when(true.B) { cnt.inc() } when(cnt.value === UInt(max-1)) { stop() } } class EnableTester(seed: Int) extends BasicTester { - val ens = Reg(init = UInt(seed)) + val ens = Reg(init = seed.asUInt) ens := ens >> 1 val (cntEnVal, _) = Counter(ens(0), 32) - val (_, done) = Counter(Bool(true), 33) + val (_, done) = Counter(true.B, 33) when(done) { assert(cntEnVal === UInt(popCount(seed))) @@ -31,7 +31,7 @@ class EnableTester(seed: Int) extends BasicTester { } class WrapTester(max: Int) extends BasicTester { - val (cnt, wrap) = Counter(Bool(true), max) + val (cnt, wrap) = Counter(true.B, max) when(wrap) { assert(cnt === UInt(max - 1)) stop() diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala index b50a80c0..ff73a676 100644 --- a/src/test/scala/chiselTests/Decoder.scala +++ b/src/test/scala/chiselTests/Decoder.scala @@ -12,7 +12,7 @@ import chisel3.util._ class Decoder(bitpats: List[String]) extends Module { val io = IO(new Bundle { - val inst = Input(UInt.width(32)) + val inst = Input(UInt(32.W)) val matched = Output(Bool()) }) io.matched := Vec(bitpats.map(BitPat(_) === io.inst)).reduce(_||_) @@ -20,11 +20,11 @@ class Decoder(bitpats: List[String]) extends Module { class DecoderTester(pairs: List[(String, String)]) extends BasicTester { val (insts, bitpats) = pairs.unzip - val (cnt, wrap) = Counter(Bool(true), pairs.size) + val (cnt, wrap) = Counter(true.B, pairs.size) val dut = Module(new Decoder(bitpats)) - dut.io.inst := Vec(insts.map(UInt(_)))(cnt) + dut.io.inst := Vec(insts.map(_.asUInt))(cnt) when(!dut.io.matched) { - assert(cnt === UInt(0)) + assert(cnt === 0.U) stop() } when(wrap) { diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala index 949b92ed..c3400013 100644 --- a/src/test/scala/chiselTests/Direction.scala +++ b/src/test/scala/chiselTests/Direction.scala @@ -9,17 +9,17 @@ import chisel3.testers.BasicTester class DirectionHaver extends Module { val io = IO(new Bundle { - val in = Input(UInt.width(32)) - val out = Output(UInt.width(32)) + val in = Input(UInt(32.W)) + val out = Output(UInt(32.W)) }) } class GoodDirection extends DirectionHaver { - io.out := UInt(0) + io.out := 0.U } class BadDirection extends DirectionHaver { - io.in := UInt(0) + io.in := 0.U } class DirectionSpec extends ChiselPropSpec with ShouldMatchers { diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala index 5f3e0dd1..6dc4aac6 100644 --- a/src/test/scala/chiselTests/EnableShiftRegister.scala +++ b/src/test/scala/chiselTests/EnableShiftRegister.scala @@ -6,14 +6,14 @@ import chisel3.testers.BasicTester class EnableShiftRegister extends Module { val io = IO(new Bundle { - val in = Input(UInt.width(4)) + val in = Input(UInt(4.W)) val shift = Input(Bool()) - val out = Output(UInt.width(4)) + val out = Output(UInt(4.W)) }) - val r0 = Reg(init = UInt(0, 4)) - val r1 = Reg(init = UInt(0, 4)) - val r2 = Reg(init = UInt(0, 4)) - val r3 = Reg(init = UInt(0, 4)) + val r0 = Reg(init = 0.U(4.W)) + val r1 = Reg(init = 0.U(4.W)) + val r2 = Reg(init = 0.U(4.W)) + val r3 = Reg(init = 0.U(4.W)) when(io.shift) { r0 := io.in r1 := r0 diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala index d683ce34..c20d26ad 100644 --- a/src/test/scala/chiselTests/GCD.scala +++ b/src/test/scala/chiselTests/GCD.scala @@ -9,14 +9,14 @@ import org.scalatest.prop._ class GCD extends Module { val io = IO(new Bundle { - val a = Input(UInt.width(32)) - val b = Input(UInt.width(32)) + val a = Input(UInt(32.W)) + val b = Input(UInt(32.W)) val e = Input(Bool()) - val z = Output(UInt.width(32)) + val z = Output(UInt(32.W)) val v = Output(Bool()) }) - val x = Reg(UInt.width( 32)) - val y = Reg(UInt.width( 32)) + val x = Reg(UInt(32.W)) + val y = Reg(UInt(32.W)) when (x > y) { x := x -% y } .otherwise { y := y -% x } when (io.e) { x := io.a; y := io.b } @@ -30,7 +30,7 @@ class GCDTester(a: Int, b: Int, z: Int) extends BasicTester { dut.io.a := a.U dut.io.b := b.U dut.io.e := first - when(first) { first := Bool(false) } + when(first) { first := false.B } when(!first && dut.io.v) { assert(dut.io.z === z.U) stop() diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala index 552fe776..521e895d 100644 --- a/src/test/scala/chiselTests/IOCompatibility.scala +++ b/src/test/scala/chiselTests/IOCompatibility.scala @@ -7,19 +7,19 @@ import chisel3.core.Binding.BindingException import org.scalatest._ class IOCSimpleIO extends Bundle { - val in = Input(UInt(width=32)) - val out = Output(UInt(width=32)) + val in = Input(UInt(32.W)) + val out = Output(UInt(32.W)) } class IOCPlusOne extends Module { val io = IO(new IOCSimpleIO) - io.out := io.in + UInt(1) + io.out := io.in + 1.U } class IOCModuleVec(val n: Int) extends Module { val io = IO(new Bundle { - val ins = Vec(n, Input(UInt(width=32))) - val outs = Vec(n, Output(UInt(width=32))) + val ins = Vec(n, Input(UInt(32.W))) + val outs = Vec(n, Output(UInt(32.W))) }) val pluses = Vec.fill(n){ Module(new IOCPlusOne).io } for (i <- 0 until n) { diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala index b13b67e3..09beddb9 100644 --- a/src/test/scala/chiselTests/LFSR16.scala +++ b/src/test/scala/chiselTests/LFSR16.scala @@ -9,9 +9,9 @@ import chisel3.util._ class LFSR16 extends Module { val io = IO(new Bundle { val inc = Input(Bool()) - val out = Output(UInt.width(16)) + val out = Output(UInt(16.W)) }) - val res = Reg(init = UInt(1, 16)) + val res = Reg(init = 1.U(16.W)) when (io.inc) { val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1)) res := nxt_res diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala index 1d09f3c5..befbf010 100644 --- a/src/test/scala/chiselTests/MemorySearch.scala +++ b/src/test/scala/chiselTests/MemorySearch.scala @@ -7,21 +7,21 @@ import chisel3.testers.BasicTester class MemorySearch extends Module { val io = IO(new Bundle { - val target = Input(UInt.width(4)) + val target = Input(UInt(4.W)) val en = Input(Bool()) val done = Output(Bool()) - val address = Output(UInt.width(3)) + val address = Output(UInt(3.W)) }) val vals = Array(0, 4, 15, 14, 2, 5, 13) - val index = Reg(init = UInt(0, width = 3)) + val index = Reg(init = 0.U(3.W)) val elts = Vec(vals.map(UInt(_,4))) - // val elts = Mem(UInt(width = 32), 8) TODO ???? + // val elts = Mem(UInt(32.W), 8) TODO ???? val elt = elts(index) - val end = !io.en && ((elt === io.target) || (index === UInt(7))) + val end = !io.en && ((elt === io.target) || (index === 7.U)) when (io.en) { - index := UInt(0) + index := 0.U } .elsewhen (!end) { - index := index +% UInt(1) + index := index +% 1.U } io.done := end io.address := index diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index c902d073..4f043f0a 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -5,8 +5,8 @@ package chiselTests import chisel3._ class SimpleIO extends Bundle { - val in = Input(UInt.width(32)) - val out = Output(UInt.width(32)) + val in = Input(UInt(32.W)) + val out = Output(UInt(32.W)) } class PlusOne extends Module { @@ -16,8 +16,8 @@ class PlusOne extends Module { class ModuleVec(val n: Int) extends Module { val io = IO(new Bundle { - val ins = Input(Vec(n, UInt(32))) - val outs = Output(Vec(n, UInt(32))) + val ins = Input(Vec(n, 32.U)) + val outs = Output(Vec(n, 32.U)) }) val pluses = Vec.fill(n){ Module(new PlusOne).io } for (i <- 0 until n) { diff --git a/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala b/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala index f8206b9c..27cf4a5f 100644 --- a/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala +++ b/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala @@ -6,13 +6,13 @@ class ModuleExplicitResetSpec extends ChiselFlatSpec { "A Module with an explicit reset in compatibility mode" should "elaborate" in { import Chisel._ - val myReset = Bool(true) + val myReset = true.B class ModuleExplicitReset(reset: Bool) extends Module(_reset = reset) { val io = new Bundle { val done = Bool(OUTPUT) } - io.done := Bool(false) + io.done := false.B } elaborate { @@ -22,13 +22,13 @@ class ModuleExplicitResetSpec extends ChiselFlatSpec { "A Module with an explicit reset in non-compatibility mode" should "elaborate" in { import chisel3._ - val myReset = Bool(true) + val myReset = true.B class ModuleExplicitReset(reset: Bool) extends Module(_reset = reset) { val io = IO(new Bundle { - val done = Bool(OUTPUT) + val done = Output(Bool()) }) - io.done := Bool(false) + io.done := false.B } elaborate { diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala index 26ee4e03..f0b2aa21 100644 --- a/src/test/scala/chiselTests/MulLookup.scala +++ b/src/test/scala/chiselTests/MulLookup.scala @@ -9,8 +9,8 @@ import chisel3.testers.BasicTester class MulLookup(val w: Int) extends Module { val io = IO(new Bundle { - val x = Input(UInt.width(w)) - val y = Input(UInt.width(w)) + val x = Input(UInt(w.W)) + val y = Input(UInt(w.W)) val z = Output(UInt.width(2 * w)) }) val tbl = Vec( @@ -24,8 +24,8 @@ class MulLookup(val w: Int) extends Module { class MulLookupTester(w: Int, x: Int, y: Int) extends BasicTester { val dut = Module(new MulLookup(w)) - dut.io.x := UInt(x) - dut.io.y := UInt(y) + dut.io.x := x.asUInt + dut.io.y := y.asUInt assert(dut.io.z === UInt(x * y)) stop() } diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala index 397ea4c2..fbe57da5 100644 --- a/src/test/scala/chiselTests/MultiAssign.scala +++ b/src/test/scala/chiselTests/MultiAssign.scala @@ -9,10 +9,10 @@ import chisel3.testers.BasicTester import chisel3.util._ class LastAssignTester() extends BasicTester { - val countOnClockCycles = Bool(true) + val countOnClockCycles = true.B val (cnt, wrap) = Counter(countOnClockCycles,2) - val test = Wire(UInt.width(4)) + val test = Wire(UInt(4.W)) assert(test === 7.U) // allow read references before assign references test := 13.U diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala index 8e4c7579..d1b9152d 100644 --- a/src/test/scala/chiselTests/OptionBundle.scala +++ b/src/test/scala/chiselTests/OptionBundle.scala @@ -20,7 +20,7 @@ class OptionBundleModule(hasIn: Boolean) extends Module { if (hasIn) { io.out := io.in.get } else { - io.out := Bool(false) + io.out := false.B } } @@ -33,14 +33,14 @@ class SomeOptionBundleTester(expected: Boolean) extends BasicTester { class NoneOptionBundleTester() extends BasicTester { val mod = Module(new OptionBundleModule(false)) - assert(mod.io.out === Bool(false)) + assert(mod.io.out === false.B) stop() } class InvalidOptionBundleTester() extends BasicTester { val mod = Module(new OptionBundleModule(false)) - mod.io.in.get := Bool(true) - assert(Bool(false)) + mod.io.in.get := true.B + assert(false.B) stop() } diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala index 42df6802..6f256b64 100644 --- a/src/test/scala/chiselTests/Padding.scala +++ b/src/test/scala/chiselTests/Padding.scala @@ -6,9 +6,9 @@ import chisel3._ class Padder extends Module { val io = IO(new Bundle { - val a = Input(UInt.width(4)) - val asp = Output(SInt.width(8)) - val aup = Output(UInt.width(8)) + val a = Input(UInt(4.W)) + val asp = Output(SInt(8.W)) + val aup = Output(UInt(8.W)) }) io.asp := io.a.asSInt io.aup := io.a.asUInt diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala index 14b21631..028b5baf 100644 --- a/src/test/scala/chiselTests/ParameterizedModule.scala +++ b/src/test/scala/chiselTests/ParameterizedModule.scala @@ -26,10 +26,10 @@ class ParameterizedModuleTester() extends BasicTester { val invert = Module(new ParameterizedModule(true)) val noninvert = Module(new ParameterizedModule(false)) - invert.io.in := Bool(true) - noninvert.io.in := Bool(true) - assert(invert.io.out === Bool(false)) - assert(noninvert.io.out === Bool(true)) + invert.io.in := true.B + noninvert.io.in := true.B + assert(invert.io.out === false.B) + assert(noninvert.io.out === true.B) stop() } diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala index 12564a40..62784cff 100644 --- a/src/test/scala/chiselTests/PrintableSpec.scala +++ b/src/test/scala/chiselTests/PrintableSpec.scala @@ -67,7 +67,7 @@ class PrintableSpec extends FlatSpec with Matchers { } it should "generate proper printf for simple Decimal printing" in { class MyModule extends BasicTester { - val myWire = Wire(init = UInt(1234)) + val myWire = Wire(init = 1234.U) printf(p"myWire = ${Decimal(myWire)}") } val firrtl = Driver.emit(() => new MyModule) @@ -78,7 +78,7 @@ class PrintableSpec extends FlatSpec with Matchers { } it should "handle printing literals" in { class MyModule extends BasicTester { - printf(Decimal(UInt(10, 32))) + printf(Decimal(10.U(32.W))) } val firrtl = Driver.emit(() => new MyModule) getPrintfs(firrtl) match { @@ -102,11 +102,11 @@ class PrintableSpec extends FlatSpec with Matchers { // parent module class MySubModule extends Module { val io = new Bundle { - val fizz = UInt(width = 32) + val fizz = UInt(32.W) } } class MyBundle extends Bundle { - val foo = UInt(width = 32) + val foo = UInt(32.W) override def cloneType = (new MyBundle).asInstanceOf[this.type] } class MyModule extends BasicTester { @@ -129,7 +129,7 @@ class PrintableSpec extends FlatSpec with Matchers { it should "handle printing ports of submodules" in { class MySubModule extends Module { val io = new Bundle { - val fizz = UInt(width = 32) + val fizz = UInt(32.W) } } class MyModule extends BasicTester { @@ -144,8 +144,8 @@ class PrintableSpec extends FlatSpec with Matchers { } it should "print UInts and SInts as Decimal by default" in { class MyModule extends BasicTester { - val myUInt = Wire(init = UInt(0)) - val mySInt = Wire(init = SInt(-1)) + val myUInt = Wire(init = 0.U) + val mySInt = Wire(init = -1.S) printf(p"$myUInt & $mySInt") } val firrtl = Driver.emit(() => new MyModule) @@ -156,8 +156,8 @@ class PrintableSpec extends FlatSpec with Matchers { } it should "print Vecs like Scala Seqs by default" in { class MyModule extends BasicTester { - val myVec = Wire(Vec(4, UInt(width = 32))) - myVec foreach (_ := UInt(0)) + val myVec = Wire(Vec(4, UInt(32.W))) + myVec foreach (_ := 0.U) printf(p"$myVec") } val firrtl = Driver.emit(() => new MyModule) @@ -170,11 +170,11 @@ class PrintableSpec extends FlatSpec with Matchers { it should "print Bundles like Scala Maps by default" in { class MyModule extends BasicTester { val myBun = Wire(new Bundle { - val foo = UInt(width = 32) - val bar = UInt(width = 32) + val foo = UInt(32.W) + val bar = UInt(32.W) }) - myBun.foo := UInt(0) - myBun.bar := UInt(0) + myBun.foo := 0.U + myBun.bar := 0.U printf(p"$myBun") } val firrtl = Driver.emit(() => new MyModule) diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala index 28b6132b..6a0569a2 100644 --- a/src/test/scala/chiselTests/Printf.scala +++ b/src/test/scala/chiselTests/Printf.scala @@ -8,7 +8,7 @@ import chisel3.util._ import chisel3.testers.BasicTester class SinglePrintfTester() extends BasicTester { - val x = UInt(254) + val x = 254.U printf("x=%x", x) stop() } @@ -19,8 +19,8 @@ class ASCIIPrintfTester() extends BasicTester { } class MultiPrintfTester() extends BasicTester { - val x = UInt(254) - val y = UInt(255) + val x = 254.U + val y = 255.U printf("x=%x y=%x", x, y) stop() } diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala index 90992c01..43e64fe7 100644 --- a/src/test/scala/chiselTests/Reg.scala +++ b/src/test/scala/chiselTests/Reg.scala @@ -17,7 +17,7 @@ class RegSpec extends ChiselFlatSpec { "A Reg" should "be of the same type and width as outType, if specified" in { class RegOutTypeWidthTester extends BasicTester { - val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt(20)) + val reg = Reg(t=UInt(2.W), next=Wire(UInt(3.W)), init=20.U) reg.getWidth should be (2) } elaborate{ new RegOutTypeWidthTester } @@ -25,13 +25,13 @@ class RegSpec extends ChiselFlatSpec { "A Reg" should "be of unknown width if outType is not specified and width is not forced" in { class RegUnknownWidthTester extends BasicTester { - val reg1 = Reg(next=Wire(UInt(width=3)), init=UInt(20)) + val reg1 = Reg(next=Wire(UInt(3.W)), init=20.U) reg1.isWidthKnown should be (false) DataMirror.widthOf(reg1).known should be (false) - val reg2 = Reg(init=UInt(20)) + val reg2 = Reg(init=20.U) reg2.isWidthKnown should be (false) DataMirror.widthOf(reg2).known should be (false) - val reg3 = Reg(next=Wire(UInt(width=3)), init=UInt(5)) + val reg3 = Reg(next=Wire(UInt(3.W)), init=5.U) reg3.isWidthKnown should be (false) DataMirror.widthOf(reg3).known should be (false) } @@ -40,7 +40,7 @@ class RegSpec extends ChiselFlatSpec { "A Reg" should "be of width of init if outType and next are missing and init is a literal of forced width" in { class RegForcedWidthTester extends BasicTester { - val reg2 = Reg(init=UInt(20, width=7)) + val reg2 = Reg(init=20.U(7.W)) reg2.getWidth should be (7) } elaborate{ new RegForcedWidthTester } diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala index 6d5a0a76..ae99df59 100644 --- a/src/test/scala/chiselTests/Risc.scala +++ b/src/test/scala/chiselTests/Risc.scala @@ -8,18 +8,18 @@ import chisel3.util._ class Risc extends Module { val io = IO(new Bundle { val isWr = Input(Bool()) - val wrAddr = Input(UInt.width(8)) - val wrData = Input(Bits.width(32)) + val wrAddr = Input(UInt(8.W)) + val wrData = Input(Bits(32.W)) val boot = Input(Bool()) val valid = Output(Bool()) - val out = Output(Bits.width(32)) + val out = Output(Bits(32.W)) }) val memSize = 256 - val file = Mem(memSize, Bits.width(32)) - val code = Mem(memSize, Bits.width(32)) - val pc = Reg(init=UInt(0, 8)) + val file = Mem(memSize, Bits(32.W)) + val code = Mem(memSize, Bits(32.W)) + val pc = Reg(init=0.U(8.W)) - val add_op :: imm_op :: Nil = Enum(Bits.width(8), 2) + val add_op :: imm_op :: Nil = Enum(Bits(8.W), 2) val inst = code(pc) val op = inst(31,24) @@ -29,16 +29,16 @@ class Risc extends Module { val ra = Mux(rai === 0.asUInt(), 0.asUInt(), file(rai)) val rb = Mux(rbi === 0.asUInt(), 0.asUInt(), file(rbi)) - val rc = Wire(Bits.width(32)) + val rc = Wire(Bits(32.W)) - io.valid := Bool(false) + io.valid := false.B io.out := 0.asUInt() rc := 0.asUInt() when (io.isWr) { code(io.wrAddr) := io.wrData } .elsewhen (io.boot) { - pc := UInt(0) + pc := 0.U } .otherwise { switch(op) { is(add_op) { rc := ra +% rb } @@ -46,7 +46,7 @@ class Risc extends Module { } io.out := rc when (rci === 255.asUInt()) { - io.valid := Bool(true) + io.valid := true.B } .otherwise { file(rci) := rc } diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala index 392c4803..900eb074 100644 --- a/src/test/scala/chiselTests/SIntOps.scala +++ b/src/test/scala/chiselTests/SIntOps.scala @@ -7,22 +7,22 @@ import chisel3.testers.BasicTester class SIntOps extends Module { val io = IO(new Bundle { - val a = Input(SInt.width(16)) - val b = Input(SInt.width(16)) - val addout = Output(SInt.width(16)) - val subout = Output(SInt.width(16)) - val timesout = Output(SInt.width(16)) - val divout = Output(SInt.width(16)) - val modout = Output(SInt.width(16)) - val lshiftout = Output(SInt.width(16)) - val rshiftout = Output(SInt.width(16)) + val a = Input(SInt(16.W)) + val b = Input(SInt(16.W)) + val addout = Output(SInt(16.W)) + val subout = Output(SInt(16.W)) + val timesout = Output(SInt(16.W)) + val divout = Output(SInt(16.W)) + val modout = Output(SInt(16.W)) + val lshiftout = Output(SInt(16.W)) + val rshiftout = Output(SInt(16.W)) val lessout = Output(Bool()) val greatout = Output(Bool()) val eqout = Output(Bool()) val noteqout = Output(Bool()) val lesseqout = Output(Bool()) val greateqout = Output(Bool()) - val negout = Output(SInt.width(16)) + val negout = Output(SInt(16.W)) }) val a = io.a @@ -32,9 +32,9 @@ class SIntOps extends Module { io.subout := a -% b // TODO: //io.timesout := (a * b)(15, 0) - //io.divout := a / Mux(b === SInt(0), SInt(1), b) + //io.divout := a / Mux(b === 0.S, 1.S, b) //io.divout := (a / b)(15, 0) - //io.modout := SInt(0) + //io.modout := 0.S //io.lshiftout := (a << 12)(15, 0) // (a << ub(3, 0))(15, 0).toSInt io.rshiftout := (a >> 8) // (a >> ub).toSInt io.lessout := a < b @@ -44,7 +44,7 @@ class SIntOps extends Module { io.lesseqout := a <= b io.greateqout := a >= b // io.negout := -a(15, 0).toSInt - io.negout := (SInt(0) -% a) + io.negout := (0.S -% a) } /* diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index a72af928..ce8fd9fc 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -12,23 +12,23 @@ class ChiselStack(val depth: Int) extends Module { val push = Input(Bool()) val pop = Input(Bool()) val en = Input(Bool()) - val dataIn = Input(UInt.width(32)) - val dataOut = Output(UInt.width(32)) + val dataIn = Input(UInt(32.W)) + val dataOut = Output(UInt(32.W)) }) - val stack_mem = Mem(depth, UInt.width(32)) + val stack_mem = Mem(depth, UInt(32.W)) val sp = Reg(init = UInt(0, width = log2Up(depth + 1))) - val out = Reg(init = UInt(0, width = 32)) + val out = Reg(init = 0.U(32.W)) when (io.en) { - when(io.push && (sp < UInt(depth))) { + when(io.push && (sp < depth.asUInt)) { stack_mem(sp) := io.dataIn - sp := sp +% UInt(1) - } .elsewhen(io.pop && (sp > UInt(0))) { - sp := sp -% UInt(1) + sp := sp +% 1.U + } .elsewhen(io.pop && (sp > 0.U)) { + sp := sp -% 1.U } - when (sp > UInt(0)) { - out := stack_mem(sp -% UInt(1)) + when (sp > 0.U) { + out := stack_mem(sp -% 1.U) } } io.dataOut := out diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index 66a06435..ccfba499 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -14,10 +14,10 @@ class Tbl(w: Int, n: Int) extends Module { val wi = Input(UInt.width(log2Up(n))) val ri = Input(UInt.width(log2Up(n))) val we = Input(Bool()) - val d = Input(UInt.width(w)) - val o = Output(UInt.width(w)) + val d = Input(UInt(w.W)) + val o = Output(UInt(w.W)) }) - val m = Mem(n, UInt.width(w)) + val m = Mem(n, UInt(w.W)) io.o := m(io.ri) when (io.we) { m(io.wi) := io.d @@ -28,17 +28,17 @@ class Tbl(w: Int, n: Int) extends Module { } class TblTester(w: Int, n: Int, idxs: List[Int], values: List[Int]) extends BasicTester { - val (cnt, wrap) = Counter(Bool(true), idxs.size) + val (cnt, wrap) = Counter(true.B, idxs.size) val dut = Module(new Tbl(w, n)) - val vvalues = Vec(values.map(UInt(_))) - val vidxs = Vec(idxs.map(UInt(_))) - val prev_idx = vidxs(cnt - UInt(1)) - val prev_value = vvalues(cnt - UInt(1)) + val vvalues = Vec(values.map(_.asUInt)) + val vidxs = Vec(idxs.map(_.asUInt)) + val prev_idx = vidxs(cnt - 1.U) + val prev_value = vvalues(cnt - 1.U) dut.io.wi := vidxs(cnt) dut.io.ri := prev_idx - dut.io.we := Bool(true) //TODO enSequence + dut.io.we := true.B //TODO enSequence dut.io.d := vvalues(cnt) - when (cnt > UInt(0)) { + when (cnt > 0.U) { when (prev_idx === vidxs(cnt)) { assert(dut.io.o === vvalues(cnt)) } .otherwise { diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala index b2e811d9..c0d64a43 100644 --- a/src/test/scala/chiselTests/TesterDriverSpec.scala +++ b/src/test/scala/chiselTests/TesterDriverSpec.scala @@ -25,13 +25,13 @@ class FinishTester extends BasicTester { // though we just set test_wire to 1, the assert below will pass because // the finish will change its value - assert(test_wire === UInt(test_wire_override_value)) + assert(test_wire === test_wire_override_value.asUInt) /** In finish we use last connect semantics to alter the test_wire in the circuit * with a new value */ override def finish(): Unit = { - test_wire := UInt(test_wire_override_value) + test_wire := test_wire_override_value.asUInt } } diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala index ad5aecd8..addd753f 100644 --- a/src/test/scala/chiselTests/UIntOps.scala +++ b/src/test/scala/chiselTests/UIntOps.scala @@ -8,15 +8,15 @@ import chisel3.testers.BasicTester class UIntOps extends Module { val io = IO(new Bundle { - val a = Input(UInt.width(16)) - val b = Input(UInt.width(16)) - val addout = Output(UInt.width(16)) - val subout = Output(UInt.width(16)) - val timesout = Output(UInt.width(16)) - val divout = Output(UInt.width(16)) - val modout = Output(UInt.width(16)) - val lshiftout = Output(UInt.width(16)) - val rshiftout = Output(UInt.width(16)) + val a = Input(UInt(16.W)) + val b = Input(UInt(16.W)) + val addout = Output(UInt(16.W)) + val subout = Output(UInt(16.W)) + val timesout = Output(UInt(16.W)) + val divout = Output(UInt(16.W)) + val modout = Output(UInt(16.W)) + val lshiftout = Output(UInt(16.W)) + val rshiftout = Output(UInt(16.W)) val lessout = Output(Bool()) val greatout = Output(Bool()) val eqout = Output(Bool()) @@ -31,10 +31,10 @@ class UIntOps extends Module { io.addout := a +% b io.subout := a -% b io.timesout := (a * b)(15, 0) - io.divout := a / Mux(b === UInt(0), UInt(1), b) + io.divout := a / Mux(b === 0.U, 1.U, b) // io.modout := a % b // TODO: - io.modout := UInt(0) + io.modout := 0.U io.lshiftout := (a << b(3, 0))(15, 0) io.rshiftout := a >> b io.lessout := a < b @@ -78,7 +78,7 @@ class UIntOpsTester(c: UIntOps) extends Tester(c) { class GoodBoolConversion extends Module { val io = IO(new Bundle { - val u = Input(UInt.width(1)) + val u = Input(UInt(1.W)) val b = Output(Bool()) }) io.b := io.u.toBool @@ -86,7 +86,7 @@ class GoodBoolConversion extends Module { class BadBoolConversion extends Module { val io = IO(new Bundle { - val u = Input(UInt.width( 5)) + val u = Input(UInt(5.W)) val b = Output(Bool()) }) io.b := io.u.toBool diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index 0d5a2188..90e337a8 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -13,7 +13,7 @@ import chisel3.util._ class ValueTester(w: Int, values: List[Int]) extends BasicTester { val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error? for ((a,b) <- v.zip(values)) { - assert(a === UInt(b)) + assert(a === b.asUInt) } stop() } @@ -31,12 +31,12 @@ class TabulateTester(n: Int) extends BasicTester { } class ShiftRegisterTester(n: Int) extends BasicTester { - val (cnt, wrap) = Counter(Bool(true), n*2) + val (cnt, wrap) = Counter(true.B, n*2) val shifter = Reg(Vec(n, UInt.width(log2Up(n)))) (shifter, shifter drop 1).zipped.foreach(_ := _) shifter(n-1) := cnt - when (cnt >= UInt(n)) { - val expected = cnt - UInt(n) + when (cnt >= n.asUInt) { + val expected = cnt - n.asUInt assert(shifter(0) === expected) } when (wrap) { diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala index b8e3a154..bcf59e03 100644 --- a/src/test/scala/chiselTests/VectorPacketIO.scala +++ b/src/test/scala/chiselTests/VectorPacketIO.scala @@ -19,7 +19,7 @@ import chisel3.util._ * IMPORTANT: The canonical way to initialize a decoupled inteface is still being debated. */ class Packet extends Bundle { - val header = UInt.width(1) + val header = UInt(1.W) } /** diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala index 00b1e7de..c474430b 100644 --- a/src/test/scala/chiselTests/VendingMachine.scala +++ b/src/test/scala/chiselTests/VendingMachine.scala @@ -11,7 +11,7 @@ class VendingMachine extends Module { val dime = Input(Bool()) val valid = Output(Bool()) }) - val c = UInt(5, width = 3) + val c = 5.U(3.W) val sIdle :: s5 :: s10 :: s15 :: sOk :: Nil = Enum(UInt(), 5) val state = Reg(init = sIdle) when (state === sIdle) { diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala index 6dc2dbac..d4491e13 100644 --- a/src/test/scala/chiselTests/When.scala +++ b/src/test/scala/chiselTests/When.scala @@ -11,44 +11,44 @@ import chisel3.util._ class WhenTester() extends BasicTester { val cnt = Counter(4) - when(Bool(true)) { cnt.inc() } - - val out = Wire(UInt.width(3)) - when(cnt.value === UInt(0)) { - out := UInt(1) - } .elsewhen (cnt.value === UInt(1)) { - out := UInt(2) - } .elsewhen (cnt.value === UInt(2)) { - out := UInt(3) + when(true.B) { cnt.inc() } + + val out = Wire(UInt(3.W)) + when(cnt.value === 0.U) { + out := 1.U + } .elsewhen (cnt.value === 1.U) { + out := 2.U + } .elsewhen (cnt.value === 2.U) { + out := 3.U } .otherwise { - out := UInt(0) + out := 0.U } - assert(out === cnt.value + UInt(1)) + assert(out === cnt.value + 1.U) - when(cnt.value === UInt(3)) { + when(cnt.value === 3.U) { stop() } } class OverlappedWhenTester() extends BasicTester { val cnt = Counter(4) - when(Bool(true)) { cnt.inc() } - - val out = Wire(UInt.width(3)) - when(cnt.value <= UInt(0)) { - out := UInt(1) - } .elsewhen (cnt.value <= UInt(1)) { - out := UInt(2) - } .elsewhen (cnt.value <= UInt(2)) { - out := UInt(3) + when(true.B) { cnt.inc() } + + val out = Wire(UInt(3.W)) + when(cnt.value <= 0.U) { + out := 1.U + } .elsewhen (cnt.value <= 1.U) { + out := 2.U + } .elsewhen (cnt.value <= 2.U) { + out := 3.U } .otherwise { - out := UInt(0) + out := 0.U } - assert(out === cnt.value + UInt(1)) + assert(out === cnt.value + 1.U) - when(cnt.value === UInt(3)) { + when(cnt.value === 3.U) { stop() } } diff --git a/src/test/scala/cookbook/Bundle2UInt.scala b/src/test/scala/cookbook/Bundle2UInt.scala index d74218a8..cb9498d1 100644 --- a/src/test/scala/cookbook/Bundle2UInt.scala +++ b/src/test/scala/cookbook/Bundle2UInt.scala @@ -11,17 +11,17 @@ import chisel3._ class Bundle2UInt extends CookbookTester(0) { // Example class MyBundle extends Bundle { - val foo = UInt(width = 4) - val bar = UInt(width = 4) + val foo = UInt(4.W) + val bar = UInt(4.W) } val bundle = Wire(new MyBundle) - bundle.foo := UInt(0xc) - bundle.bar := UInt(0x3) + bundle.foo := 0xc.U + bundle.bar := 0x3.U val uint = bundle.asUInt printf(p"$uint") // 195 // Test - assert(uint === UInt(0xc3)) + assert(uint === 0xc3.U) } class Bundle2UIntSpec extends CookbookSpec { diff --git a/src/test/scala/cookbook/CookbookSpec.scala b/src/test/scala/cookbook/CookbookSpec.scala index b244f3cf..6ecea446 100644 --- a/src/test/scala/cookbook/CookbookSpec.scala +++ b/src/test/scala/cookbook/CookbookSpec.scala @@ -18,7 +18,7 @@ abstract class CookbookTester(length: Int) extends BasicTester { // No IO allowed, cookbook tests must be self-contained override final val io = new Bundle { } - val (cycle, done) = Counter(Bool(true), length) + val (cycle, done) = Counter(true.B, length) when (done) { stop() } } diff --git a/src/test/scala/cookbook/UInt2Bundle.scala b/src/test/scala/cookbook/UInt2Bundle.scala index fbf7fe8a..3ce4eebf 100644 --- a/src/test/scala/cookbook/UInt2Bundle.scala +++ b/src/test/scala/cookbook/UInt2Bundle.scala @@ -11,16 +11,16 @@ import chisel3._ class UInt2Bundle extends CookbookTester(0) { // Example class MyBundle extends Bundle { - val foo = UInt(width = 4) - val bar = UInt(width = 4) + val foo = UInt(4.W) + val bar = UInt(4.W) } - val uint = UInt(0xb4) + val uint = 0xb4.U val bundle = (new MyBundle).fromBits(uint) printf(p"$bundle") // Bundle(foo -> 11, bar -> 4) // Test - assert(bundle.foo === UInt(0xb)) - assert(bundle.bar === UInt(0x4)) + assert(bundle.foo === 0xb.U) + assert(bundle.bar === 0x4.U) } class UInt2BundleSpec extends CookbookSpec { diff --git a/src/test/scala/cookbook/UInt2VecOfBool.scala b/src/test/scala/cookbook/UInt2VecOfBool.scala index ad4a0334..09d538f9 100644 --- a/src/test/scala/cookbook/UInt2VecOfBool.scala +++ b/src/test/scala/cookbook/UInt2VecOfBool.scala @@ -11,15 +11,15 @@ import chisel3._ */ class UInt2VecOfBool extends CookbookTester(0) { // Example - val uint = UInt(0xc) + val uint = 0xc.U val vec = Vec(uint.toBools) printf(p"$vec") // Vec(0, 0, 1, 1) // Test - assert(vec(0) === Bool(false)) - assert(vec(1) === Bool(false)) - assert(vec(2) === Bool(true)) - assert(vec(3) === Bool(true)) + assert(vec(0) === false.B) + assert(vec(1) === false.B) + assert(vec(2) === true.B) + assert(vec(3) === true.B) } class UInt2VecOfBoolSpec extends CookbookSpec { diff --git a/src/test/scala/cookbook/VecOfBool2UInt.scala b/src/test/scala/cookbook/VecOfBool2UInt.scala index 5852120c..531e4e68 100644 --- a/src/test/scala/cookbook/VecOfBool2UInt.scala +++ b/src/test/scala/cookbook/VecOfBool2UInt.scala @@ -10,7 +10,7 @@ import chisel3._ */ class VecOfBool2UInt extends CookbookTester(0) { // Example - val vec = Vec(Bool(true), Bool(false), Bool(true), Bool(true)) + val vec = Vec(true.B, false.B, true.B, true.B) val uint = vec.asUInt printf(p"$uint") // 13 @@ -18,7 +18,7 @@ class VecOfBool2UInt extends CookbookTester(0) { * * (remember leftmost Bool in Vec is low order bit) */ - assert(UInt(0xd) === uint) + assert(0xd.U === uint) } class VecOfBool2UIntSpec extends CookbookSpec { |