6 files changed, 22 insertions, 14 deletions
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index 88aaf06c..8848d4f5 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -20,6 +20,10 @@ class ChiselFlatSpec extends FlatSpec with ChiselRunners with Matchers
 /** Spec base class for property-based testers. */
 class ChiselPropSpec extends PropSpec with ChiselRunners with PropertyChecks {
 
+  // Constrain the default number of instances generated for every use of forAll.
+  implicit override val generatorDrivenConfig =
+    PropertyCheckConfig(minSuccessful = 8, minSize = 1, maxSize = 4)
+
   // Generator for small positive integers.
   val smallPosInts = Gen.choose(1, 4)
 
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index 64fc8bda..bbd3d6c2 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -41,7 +41,7 @@ class ComplexAssignTester(enList: List[Boolean], re: Int, im: Int) extends Basic
     io.done := Bool(true); io.error := cnt
   } .elsewhen(wrap) { io.done := Bool(true) }
 }
-   
+
 class ComplexAssignSpec extends ChiselPropSpec {
 
   property("All complex assignments should return the correct result") {
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index acc1e84e..f2efbcd5 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -38,7 +38,7 @@ class GCDTester(a: Int, b: Int, z: Int) extends BasicTester {
 }
 
 class GCDSpec extends ChiselPropSpec {
-  
+
   //TODO: use generators and this function to make z's
   def gcd(a: Int, b: Int): Int = if(b == 0) a else gcd(b, a%b)
 
diff --git a/src/test/scala/chiselTests/Harness.scala b/src/test/scala/chiselTests/Harness.scala
index 98ad3b11..31a219e4 100644
--- a/src/test/scala/chiselTests/Harness.scala
+++ b/src/test/scala/chiselTests/Harness.scala
@@ -1,13 +1,15 @@
+// See LICENSE for license details.
+
 package chiselTests
 import Chisel.testers.BasicTester
 import org.scalatest._
 import org.scalatest.prop._
 import java.io.File
 
-class HarnessSpec extends ChiselPropSpec 
+class HarnessSpec extends ChiselPropSpec
   with Chisel.BackendCompilationUtilities {
 
-  def makeTrivialVerilog = makeHarness((prefix: String) => s"""
+  def makeTrivialVerilog: (File => File) = makeHarness((prefix: String) => s"""
 module ${prefix};
   initial begin
     $$display("$prefix!");
@@ -16,7 +18,7 @@ module ${prefix};
 endmodule
 """, ".v") _
 
-  def makeFailingVerilog = makeHarness((prefix: String) => s"""
+  def makeFailingVerilog: (File => File) = makeHarness((prefix: String) => s"""
 module $prefix;
   initial begin
     assert (1 == 0) else $$error("My specific, expected error message!");
@@ -26,7 +28,7 @@ module $prefix;
 endmodule
 """, ".v") _
 
-  def makeCppHarness = makeHarness((prefix: String) => s"""
+  def makeCppHarness: (File => File) = makeHarness((prefix: String) => s"""
 #include "V$prefix.h"
 #include "verilated.h"
 
@@ -72,4 +74,4 @@ int main(int argc, char **argv, char **env) {
     assert(!executeExpectingFailure(prefix, dir, "A string that doesn't match any test output"))
   }
 }
- 
+
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 77d10d98..55c92b45 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -18,7 +18,7 @@ class RegSpec extends ChiselFlatSpec {
       val reg = Reg(t=UInt(width=2), next=UInt(width=3), init=UInt(20))
       reg.width.get should be (2)
     }
-    assert(execute{new RegOutTypeWidthTester})
+    elaborate{ new RegOutTypeWidthTester }
   }
 
   "A Reg" should "be of unknown width if outType is not specified and width is not forced" in {
@@ -30,7 +30,7 @@ class RegSpec extends ChiselFlatSpec {
       val reg3 = Reg(next=UInt(width=3), init=UInt(width=5))
       reg3.width.known should be (false)
     }
-    assert(execute{new RegUnknownWidthTester})
+    elaborate { new RegUnknownWidthTester }
   }
 
   "A Reg" should "be of width of init if outType and next are missing and init is a literal of forced width" in {
@@ -38,6 +38,6 @@ class RegSpec extends ChiselFlatSpec {
       val reg2 = Reg(init=UInt(20, width=7))
       reg2.width.get should be (7)
     }
-    assert(execute{new RegForcedWidthTester})
+    elaborate{ new RegForcedWidthTester }
   }
 }
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index 40f71c69..a3b1feb0 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -9,8 +9,8 @@ import Chisel.testers.BasicTester
 
 class Tbl(w: Int, n: Int) extends Module {
   val io = new Bundle {
-    val wi  = UInt(INPUT, log2Ceil(w))
-    val ri  = UInt(INPUT, log2Ceil(w))
+    val wi  = UInt(INPUT, log2Up(n))
+    val ri  = UInt(INPUT, log2Up(n))
     val we  = Bool(INPUT)
     val  d  = UInt(INPUT, w)
     val  o  = UInt(OUTPUT, w)
@@ -42,8 +42,10 @@ class TblSpec extends ChiselPropSpec {
 
   property("All table reads should return the previous write") {
     forAll(safeUIntPairN(8)) { case(w: Int, pairs: List[(Int, Int)]) =>
-      val (idxs, values) = pairs.unzip
-      assert(execute{ new TblTester(w, 1 << w, idxs, values) })
+      whenever(w > 0) {
+        val (idxs, values) = pairs.unzip
+        assert(execute{ new TblTester(w, 1 << w, idxs, values) })
+      }
     }
   }
 }