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-rw-r--r--src/test/scala/chiselTests/BundleWire.scala28
-rw-r--r--src/test/scala/chiselTests/DriverSpec.scala33
-rw-r--r--src/test/scala/chiselTests/Reg.scala1
-rw-r--r--src/test/scala/chiselTests/Vec.scala6
4 files changed, 65 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 53d46e93..5b38ff6e 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -24,6 +24,27 @@ class BundleWire(n: Int) extends Module {
}
}
+class BundleToUnitTester extends BasicTester {
+ val bundle1 = Wire(new Bundle {
+ val a = UInt(width = 4)
+ val b = UInt(width = 4)
+ })
+ val bundle2 = Wire(new Bundle {
+ val a = UInt(width = 2)
+ val b = UInt(width = 6)
+ })
+
+ // 0b00011011 split as 0001 1011 and as 00 011011
+ bundle1.a := 1.U
+ bundle1.b := 11.U
+ bundle2.a := 0.U
+ bundle2.b := 27.U
+
+ assert(bundle1.asUInt() === bundle2.asUInt())
+
+ stop()
+}
+
class BundleWireTester(n: Int, x: Int, y: Int) extends BasicTester {
val dut = Module(new BundleWire(n))
dut.io.in.x := UInt(x)
@@ -43,3 +64,10 @@ class BundleWireSpec extends ChiselPropSpec {
}
}
}
+
+class BundleToUIntSpec extends ChiselPropSpec {
+ property("Bundles with same data but different, underlying elements should compare as UInt") {
+ assertTesterPasses( new BundleToUnitTester )
+ }
+}
+
diff --git a/src/test/scala/chiselTests/DriverSpec.scala b/src/test/scala/chiselTests/DriverSpec.scala
new file mode 100644
index 00000000..4f9619e3
--- /dev/null
+++ b/src/test/scala/chiselTests/DriverSpec.scala
@@ -0,0 +1,33 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import chisel3._
+
+import org.scalatest.{Matchers, FreeSpec}
+
+class DummyModule extends Module {
+ val io = IO(new Bundle {
+ val in = UInt(INPUT, 1)
+ val out = UInt(OUTPUT, 1)
+ })
+ io.out := io.in
+}
+
+class DriverSpec extends FreeSpec with Matchers {
+ "Driver's execute methods are used to run chisel and firrtl" - {
+ "options can be picked up from comand line with no args" in {
+ Driver.execute(Array.empty[String], () => new DummyModule)
+ }
+ "options can be picked up from comand line setting top name" in {
+ Driver.execute(Array("-tn", "dm", "-td", "local-build"), () => new DummyModule)
+ }
+ "execute returns a chisel execution result" in {
+ val args = Array("--compiler", "low")
+ val result = Driver.execute(Array.empty[String], () => new DummyModule)
+ result shouldBe a[ChiselExecutionSucccess]
+ val successResult = result.asInstanceOf[ChiselExecutionSucccess]
+ successResult.emitted should include ("circuit DummyModule")
+ }
+ }
+}
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index a9086223..90992c01 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -2,6 +2,7 @@
package chiselTests
+import firrtl.ir.Input
import org.scalatest._
import chisel3._
import chisel3.core.DataMirror
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index c5447610..0d5a2188 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -23,9 +23,9 @@ class TabulateTester(n: Int) extends BasicTester {
val x = Vec(Array.tabulate(n){ i => UInt(i * 2) })
val u = Vec.tabulate(n)(i => UInt(i*2))
- assert(v.toBits === x.toBits)
- assert(v.toBits === u.toBits)
- assert(x.toBits === u.toBits)
+ assert(v.asUInt() === x.asUInt())
+ assert(v.asUInt() === u.asUInt())
+ assert(x.asUInt() === u.asUInt())
stop()
}