4 files changed, 46 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index 83077544..57ceff3f 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -22,6 +22,8 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     val requireIOWrap = false
     val dontTryConnectionsSwapped = true
     val dontAssumeDirectionality = true
+    val deprecateOldDirectionMethods = true
+    val checkSynthesizable = true
   }
 
   class SmallBundle extends Bundle {
@@ -265,6 +267,8 @@ class CompileOptionsSpec extends ChiselFlatSpec {
         val requireIOWrap = false
         val dontTryConnectionsSwapped = true
         val dontAssumeDirectionality = true
+        val deprecateOldDirectionMethods = false
+        val checkSynthesizable = true
       }
 
     }
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index 0a1f31cc..c5a23f82 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -11,7 +11,7 @@ import chisel3.util._
 
 class Complex[T <: Data](val re: T, val im: T) extends Bundle {
   override def cloneType: this.type =
-    new Complex(re.chiselCloneType, im.chiselCloneType).asInstanceOf[this.type]
+    new Complex(re.cloneType, im.cloneType).asInstanceOf[this.type]
 }
 
 class ComplexAssign(w: Int) extends Module {
diff --git a/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala b/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala
new file mode 100644
index 00000000..f8206b9c
--- /dev/null
+++ b/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala
@@ -0,0 +1,38 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+class ModuleExplicitResetSpec extends ChiselFlatSpec  {
+
+  "A Module with an explicit reset in compatibility mode" should "elaborate" in {
+    import Chisel._
+    val myReset = Bool(true)
+    class ModuleExplicitReset(reset: Bool) extends Module(_reset = reset) {
+      val io = new Bundle {
+        val done = Bool(OUTPUT)
+      }
+
+      io.done := Bool(false)
+    }
+
+    elaborate {
+      new ModuleExplicitReset(myReset)
+    }
+  }
+
+  "A Module with an explicit reset in non-compatibility mode" should "elaborate" in {
+    import chisel3._
+    val myReset = Bool(true)
+    class ModuleExplicitReset(reset: Bool) extends Module(_reset = reset) {
+      val io = IO(new Bundle {
+        val done = Bool(OUTPUT)
+      })
+
+      io.done := Bool(false)
+    }
+
+    elaborate {
+      new ModuleExplicitReset(myReset)
+    }
+  }
+}
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index fa4c4898..397ea4c2 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -9,7 +9,8 @@ import chisel3.testers.BasicTester
 import chisel3.util._
 
 class LastAssignTester() extends BasicTester {
-  val cnt = Counter(2)
+  val countOnClockCycles = Bool(true)
+  val (cnt, wrap) = Counter(countOnClockCycles,2)
 
   val test = Wire(UInt.width(4))
   assert(test === 7.U)  // allow read references before assign references
@@ -20,7 +21,7 @@ class LastAssignTester() extends BasicTester {
   test := 7.U
   assert(test === 7.U)  // this obviously should work
 
-  when(cnt.value === 1.U) {
+  when(cnt === 1.U) {
     stop()
   }
 }