4 files changed, 113 insertions, 4 deletions
diff --git a/src/test/scala/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala
index 3414ec8a..5a5bcf67 100644
--- a/src/test/scala/chiselTests/RecordSpec.scala
+++ b/src/test/scala/chiselTests/RecordSpec.scala
@@ -284,6 +284,26 @@ class RecordSpec extends ChiselFlatSpec with RecordSpecUtils with Utils {
     testStrings.foreach(x => assert(x == "~NestedRecordModule|InnerModule>io.foo"))
   }
 
+  they should "work correctly with DataMirror in nested OpaqueType Records" in {
+    var mod: NestedRecordModule = null
+    ChiselStage.elaborate { mod = new NestedRecordModule; mod }
+    val ports = chisel3.experimental.DataMirror.fullModulePorts(mod.inst)
+    val expectedPorts = Seq(
+      ("clock", mod.inst.clock),
+      ("reset", mod.inst.reset),
+      ("io", mod.inst.io),
+      ("io_bar", mod.inst.io.bar),
+      ("io_bar", mod.inst.io.bar.k),
+      ("io_bar", mod.inst.io.bar.k.k),
+      ("io_bar", mod.inst.io.bar.k.k.elements.head._2),
+      ("io_foo", mod.inst.io.foo),
+      ("io_foo", mod.inst.io.foo.k),
+      ("io_foo", mod.inst.io.foo.k.k),
+      ("io_foo", mod.inst.io.foo.k.k.elements.head._2)
+    )
+    ports shouldBe expectedPorts
+  }
+
   they should "work correctly when connecting nested OpaqueType elements" in {
     val nestedRecordChirrtl = ChiselStage.emitChirrtl { new NestedRecordModule }
     nestedRecordChirrtl should include("input in : UInt<8>")
diff --git a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala
index ebb7cbdb..fb3f64c7 100644
--- a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala
+++ b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala
@@ -55,9 +55,11 @@ class FlatIOSpec extends ChiselFlatSpec {
       val bar = Analog(8.W)
     }
     class MyModule extends RawModule {
-      val in = IO(Flipped(new MyBundle))
-      val out = IO(new MyBundle)
-      out <> in
+      val io = FlatIO(new Bundle {
+        val in = Flipped(new MyBundle)
+        val out = new MyBundle
+      })
+      io.out <> io.in
     }
     val chirrtl = emitChirrtl(new MyModule)
     chirrtl should include("out.foo <= in.foo")
diff --git a/src/test/scala/chiselTests/util/BitSetSpec.scala b/src/test/scala/chiselTests/util/BitSetSpec.scala
index dd66ba40..cf5f54cf 100644
--- a/src/test/scala/chiselTests/util/BitSetSpec.scala
+++ b/src/test/scala/chiselTests/util/BitSetSpec.scala
@@ -110,9 +110,36 @@ class BitSetSpec extends AnyFlatSpec with Matchers {
             "b11??????"
           )
         ),
-        true
+        errorBit = true
       )
     })
   }
 
+  it should "be decoded with DontCare error" in {
+    import chisel3._
+    import chisel3.util.experimental.decode.decoder
+    // [0 - 256] part into: [0 - 31], [32 - 47, 64 - 127], [192 - 255]
+    // "0011????" "10??????" is empty to error
+    chisel3.stage.ChiselStage.emitSystemVerilog(new Module {
+      val in = IO(Input(UInt(8.W)))
+      val out = IO(Output(UInt(4.W)))
+      out := decoder.bitset(
+        in,
+        Seq(
+          BitSet.fromString(
+            "b000?????"
+          ),
+          BitSet.fromString(
+            """b0010????
+              |b01??????
+              |""".stripMargin
+          ),
+          BitSet.fromString(
+            "b11??????"
+          )
+        ),
+        errorBit = false
+      )
+    })
+  }
 }
diff --git a/src/test/scala/chiselTests/util/PriorityMuxSpec.scala b/src/test/scala/chiselTests/util/PriorityMuxSpec.scala
new file mode 100644
index 00000000..32cf2431
--- /dev/null
+++ b/src/test/scala/chiselTests/util/PriorityMuxSpec.scala
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests.util
+
+import chisel3._
+import chisel3.util.{is, switch, Counter, PriorityMux}
+import chisel3.testers.BasicTester
+import chisel3.stage.ChiselStage.emitChirrtl
+
+import chiselTests.ChiselFlatSpec
+
+class PriorityMuxTester extends BasicTester {
+
+  val sel = Wire(UInt(3.W))
+  sel := 0.U // default
+
+  val elts = Seq(5.U, 6.U, 7.U)
+  val muxed = PriorityMux(sel, elts)
+
+  // Priority is given to lowest order bit
+  val tests = Seq(
+    1.U -> elts(0),
+    2.U -> elts(1),
+    3.U -> elts(0),
+    4.U -> elts(2),
+    5.U -> elts(0),
+    6.U -> elts(1),
+    7.U -> elts(0)
+  )
+  val (cycle, done) = Counter(0 until tests.size + 1)
+
+  for (((in, out), idx) <- tests.zipWithIndex) {
+    when(cycle === idx.U) {
+      sel := in
+      assert(muxed === out)
+    }
+  }
+
+  when(done) {
+    stop()
+  }
+}
+
+class PriorityMuxSpec extends ChiselFlatSpec {
+  behavior.of("PriorityMux")
+
+  it should "be functionally correct" in {
+    assertTesterPasses(new PriorityMuxTester)
+  }
+
+  it should "be stack safe" in {
+    emitChirrtl(new RawModule {
+      val n = 1 << 15
+      val in = IO(Input(Vec(n, UInt(8.W))))
+      val sel = IO(Input(UInt(n.W)))
+      val out = IO(Output(UInt(8.W)))
+      out := PriorityMux(sel, in)
+    })
+  }
+}