1 files changed, 109 insertions, 5 deletions

diff --git a/src/test/scala/chiselTests/naming/PrefixSpec.scala b/src/test/scala/chiselTests/naming/PrefixSpec.scala
index f9a78f0e..6d52407e 100644
--- a/src/test/scala/chiselTests/naming/PrefixSpec.scala
+++ b/src/test/scala/chiselTests/naming/PrefixSpec.scala
@@ -3,6 +3,7 @@
 package chiselTests.naming
 
 import chisel3._
+import chisel3.stage.ChiselStage
 import chisel3.aop.Select
 import chisel3.experimental.{dump, noPrefix, prefix, treedump}
 import chiselTests.{ChiselPropSpec, Utils}
@@ -232,18 +233,46 @@ class PrefixSpec extends ChiselPropSpec with Utils {
     }
   }
 
-  property("Prefixing should be the prefix during the last call to autoName/suggestName") {
+  property("Prefixing should NOT be influenced by suggestName") {
     class Test extends Module {
       {
         val wire = {
-          val x = Wire(UInt(3.W)).suggestName("mywire")
-          x
+          val x = Wire(UInt(3.W)) // wire_x
+          Wire(UInt(3.W)).suggestName("foo")
+        }
+      }
+    }
+    aspectTest(() => new Test) { top: Test =>
+      Select.wires(top).map(_.instanceName) should be(List("wire_x", "foo"))
+    }
+  }
+
+  property("Prefixing should be influenced by the \"current name\" of the signal") {
+    class Test extends Module {
+      {
+        val wire = {
+          val y = Wire(UInt(3.W)).suggestName("foo")
+          val x = Wire(UInt(3.W)) // wire_x
+          y
+        }
+
+        val wire2 = Wire(UInt(3.W))
+        wire2 := {
+          val x = Wire(UInt(3.W)) // wire2_x
+          x + 1.U
+        }
+        wire2.suggestName("bar")
+
+        val wire3 = Wire(UInt(3.W))
+        wire3.suggestName("fizz")
+        wire3 := {
+          val x = Wire(UInt(3.W)) // fizz_x
+          x + 1.U
         }
       }
     }
     aspectTest(() => new Test) { top: Test =>
-      Select.wires(top).map(_.instanceName) should be(List("mywire"))
-      Select.wires(top).map(_.instanceName) shouldNot be(List("wire_mywire"))
+      Select.wires(top).map(_.instanceName) should be(List("foo", "wire_x", "bar", "wire2_x", "fizz", "fizz_x"))
     }
   }
 
@@ -391,6 +420,81 @@ class PrefixSpec extends ChiselPropSpec with Utils {
     aspectTest(() => new Test) { top: Test =>
       Select.wires(top).map(_.instanceName) should be(List("x", "x_w_w", "x_w_w_w", "x_w_w_w_w"))
     }
+  }
+
+  property("Prefixing should work for verification ops") {
+    class Test extends Module {
+      val foo, bar = IO(Input(UInt(8.W)))
+
+      {
+        val x5 = {
+          val x1 = chisel3.assert(1.U === 1.U)
+          val x2 = cover(foo =/= bar)
+          val x3 = chisel3.assume(foo =/= 123.U)
+          val x4 = printf("foo = %d\n", foo)
+          x1
+        }
+      }
+    }
+    val chirrtl = ChiselStage.emitChirrtl(new Test)
+    (chirrtl should include).regex("assert.*: x5")
+    (chirrtl should include).regex("cover.*: x5_x2")
+    (chirrtl should include).regex("assume.*: x5_x3")
+    (chirrtl should include).regex("printf.*: x5_x4")
+  }
 
+  property("Leading '_' in val names should be ignored in prefixes") {
+    class Test extends Module {
+      {
+        val a = {
+          val _b = {
+            val c = Wire(UInt(3.W))
+            4.U // literal because there is no name
+          }
+          _b
+        }
+      }
+    }
+    aspectTest(() => new Test) { top: Test =>
+      Select.wires(top).map(_.instanceName) should be(List("a_b_c"))
+    }
+  }
+
+  // This checks that we don't just blanket ignore leading _ in prefixes
+  property("User-specified prefixes with '_' should be respected") {
+    class Test extends Module {
+      {
+        val a = {
+          val _b = prefix("_b") {
+            val c = Wire(UInt(3.W))
+          }
+          4.U
+        }
+      }
+    }
+    aspectTest(() => new Test) { top: Test =>
+      Select.wires(top).map(_.instanceName) should be(List("a__b_c"))
+    }
+  }
+
+  property("Leading '_' in signal names should be ignored in prefixes from connections") {
+    class Test extends Module {
+      {
+        val a = {
+          val b = {
+            val _c = IO(Output(UInt(3.W))) // port so not selected as wire
+            _c := {
+              val d = Wire(UInt(3.W))
+              d
+            }
+            4.U // literal so there is no name
+          }
+          b
+        }
+      }
+    }
+    aspectTest(() => new Test) { top: Test =>
+      Select.wires(top).map(_.instanceName) should be(List("a_b_c_d"))
+    }
   }
 }