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Diffstat (limited to 'src/test/scala/chiselTests/VecLiteralSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/VecLiteralSpec.scala | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/test/scala/chiselTests/VecLiteralSpec.scala b/src/test/scala/chiselTests/VecLiteralSpec.scala index d11289e1..d91cd2f4 100644 --- a/src/test/scala/chiselTests/VecLiteralSpec.scala +++ b/src/test/scala/chiselTests/VecLiteralSpec.scala @@ -461,10 +461,10 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils { "vec literals can contain bundles" in { val chirrtl = (new chisel3.stage.ChiselStage).emitChirrtl(new VecExample, args = Array("--full-stacktrace")) - chirrtl should include("""out[0].bar <= UInt<5>("h016")""") - chirrtl should include("""out[0].foo <= UInt<6>("h02a")""") - chirrtl should include("""out[1].bar <= UInt<2>("h03")""") - chirrtl should include("""out[1].foo <= UInt<3>("h07")""") + chirrtl should include("""out[0].bar <= UInt<5>("h16")""") + chirrtl should include("""out[0].foo <= UInt<6>("h2a")""") + chirrtl should include("""out[1].bar <= UInt<2>("h3")""") + chirrtl should include("""out[1].foo <= UInt<3>("h7")""") } |