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-rw-r--r--src/test/scala/chiselTests/Vec.scala3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 6c62ab26..1c5157b5 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -146,6 +146,7 @@ class ZeroEntryVecTester extends BasicTester {
val m = Module(new Module {
val io = IO(Output(bundleWithZeroEntryVec))
+ io.foo := false.B
})
WireInit(m.io.bar)
@@ -179,6 +180,8 @@ class ModuleIODynamicIndexTester(n: Int) extends BasicTester {
when (cycle =/= i.U) {
m.in := 0.U // default
assert(m.out === 0.U)
+ } .otherwise {
+ m.in := DontCare
}
}
// only connect one dut per cycle