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Diffstat (limited to 'src/test/scala/chiselTests/Vec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Vec.scala | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index 5239c6ba..c5447610 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -2,10 +2,13 @@ package chiselTests -import Chisel._ import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester + +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ +//import chisel3.core.ExplicitCompileOptions.Strict class ValueTester(w: Int, values: List[Int]) extends BasicTester { val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error? @@ -29,7 +32,7 @@ class TabulateTester(n: Int) extends BasicTester { class ShiftRegisterTester(n: Int) extends BasicTester { val (cnt, wrap) = Counter(Bool(true), n*2) - val shifter = Reg(Vec(n, UInt(width = log2Up(n)))) + val shifter = Reg(Vec(n, UInt.width(log2Up(n)))) (shifter, shifter drop 1).zipped.foreach(_ := _) shifter(n-1) := cnt when (cnt >= UInt(n)) { |