summaryrefslogtreecommitdiff
path: root/src/test/scala/chiselTests/Vec.scala
diff options
context:
space:
mode:
Diffstat (limited to 'src/test/scala/chiselTests/Vec.scala')
-rw-r--r--src/test/scala/chiselTests/Vec.scala4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 145fd8f6..ea670f37 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
package chiselTests
import Chisel._
@@ -10,7 +12,7 @@ class VecSpec extends ChiselPropSpec {
class ValueTester(w: Int, values: List[Int]) extends BasicTester {
io.done := Bool(true)
val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error?
- io.error := v.zip(values).map { case(a,b) =>
+ io.error := v.zip(values).map { case(a,b) =>
a != UInt(b)
}.foldLeft(UInt(0))(_##_)
}