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Diffstat (limited to 'src/test/scala/chiselTests/Risc.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Risc.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala index 57586c97..0d03ff65 100644 --- a/src/test/scala/chiselTests/Risc.scala +++ b/src/test/scala/chiselTests/Risc.scala @@ -19,7 +19,7 @@ class Risc extends Module { val code = Mem(memSize, Bits(32.W)) val pc = Reg(init=0.U(8.W)) - val add_op :: imm_op :: Nil = Enum(Bits(8.W), 2) + val add_op :: imm_op :: Nil = Enum(2) val inst = code(pc) val op = inst(31,24) |