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Diffstat (limited to 'src/test/scala/chiselTests/ResetSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/ResetSpec.scala | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/test/scala/chiselTests/ResetSpec.scala b/src/test/scala/chiselTests/ResetSpec.scala index 77c90814..0e535964 100644 --- a/src/test/scala/chiselTests/ResetSpec.scala +++ b/src/test/scala/chiselTests/ResetSpec.scala @@ -73,14 +73,14 @@ class ResetSpec extends ChiselFlatSpec with Utils { behavior of "Users" they should "be able to force implicit reset to be synchronous" in { - val fir = ChiselStage.emitChirrtl(new MultiIOModule with RequireSyncReset { + val fir = ChiselStage.emitChirrtl(new Module with RequireSyncReset { reset shouldBe a [Bool] }) fir should include ("input reset : UInt<1>") } they should "be able to force implicit reset to be asynchronous" in { - val fir = ChiselStage.emitChirrtl(new MultiIOModule with RequireAsyncReset { + val fir = ChiselStage.emitChirrtl(new Module with RequireAsyncReset { reset shouldBe an [AsyncReset] }) fir should include ("input reset : AsyncReset") @@ -88,8 +88,8 @@ class ResetSpec extends ChiselFlatSpec with Utils { "Chisel" should "error if sync and async modules are nested" in { a [ChiselException] should be thrownBy extractCause[ChiselException] { - ChiselStage.elaborate(new MultiIOModule with RequireAsyncReset { - val mod = Module(new MultiIOModule with RequireSyncReset) + ChiselStage.elaborate(new Module with RequireAsyncReset { + val mod = Module(new Module with RequireSyncReset) }) } } |