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-rw-r--r--src/test/scala/chiselTests/MuxSpec.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/MuxSpec.scala b/src/test/scala/chiselTests/MuxSpec.scala
index a995ea76..71f4cd86 100644
--- a/src/test/scala/chiselTests/MuxSpec.scala
+++ b/src/test/scala/chiselTests/MuxSpec.scala
@@ -38,7 +38,7 @@ class MuxLookupWrapper(keyWidth: Int, default: Int, mapping: () => Seq[(UInt, UI
class MuxLookupExhaustiveSpec extends ChiselPropSpec {
val keyWidth = 2
val default = 9 // must be less than 10 to avoid hex/decimal mismatches
- val firrtlLit = s"""UInt<4>("h$default")"""
+ val firrtlLit = s"""UInt<4>("h0$default")"""
val stage = new ChiselStage
// Assumes there are no literals with 'UInt<4>("h09")' in the output FIRRTL