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Diffstat (limited to 'src/test/scala/chiselTests/MultiAssign.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MultiAssign.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala index 397ea4c2..fbe57da5 100644 --- a/src/test/scala/chiselTests/MultiAssign.scala +++ b/src/test/scala/chiselTests/MultiAssign.scala @@ -9,10 +9,10 @@ import chisel3.testers.BasicTester import chisel3.util._ class LastAssignTester() extends BasicTester { - val countOnClockCycles = Bool(true) + val countOnClockCycles = true.B val (cnt, wrap) = Counter(countOnClockCycles,2) - val test = Wire(UInt.width(4)) + val test = Wire(UInt(4.W)) assert(test === 7.U) // allow read references before assign references test := 13.U |