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Diffstat (limited to 'src/test/scala/chiselTests/LFSR16.scala')
| -rw-r--r-- | src/test/scala/chiselTests/LFSR16.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala index dcc3a403..ed76a296 100644 --- a/src/test/scala/chiselTests/LFSR16.scala +++ b/src/test/scala/chiselTests/LFSR16.scala @@ -10,8 +10,8 @@ class LFSR16 extends Module { val out = UInt(OUTPUT, 16) } val res = Reg(init = UInt(1, 16)) - when (io.inc) { - val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1)) + when (io.inc) { + val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1)) res := nxt_res } io.out := res @@ -37,7 +37,7 @@ class LFSR16Tester(c: LFSR16) extends Tester(c) { //TODO: Use chisel.util version instead? class LFSRSpec extends ChiselPropSpec { - + property("LFSR16 should elaborate") { elaborate { new LFSR16 } } |