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Diffstat (limited to 'src/test/scala/chiselTests/EnableShiftRegister.scala')
| -rw-r--r-- | src/test/scala/chiselTests/EnableShiftRegister.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala index 26af944f..5f3e0dd1 100644 --- a/src/test/scala/chiselTests/EnableShiftRegister.scala +++ b/src/test/scala/chiselTests/EnableShiftRegister.scala @@ -6,9 +6,9 @@ import chisel3.testers.BasicTester class EnableShiftRegister extends Module { val io = IO(new Bundle { - val in = Input(UInt(4)) + val in = Input(UInt.width(4)) val shift = Input(Bool()) - val out = Output(UInt(4)) + val out = Output(UInt.width(4)) }) val r0 = Reg(init = UInt(0, 4)) val r1 = Reg(init = UInt(0, 4)) |