1 files changed, 18 insertions, 27 deletions
diff --git a/src/test/scala/chiselTests/BlackBoxImpl.scala b/src/test/scala/chiselTests/BlackBoxImpl.scala
index 9871f251..da89a326 100644
--- a/src/test/scala/chiselTests/BlackBoxImpl.scala
+++ b/src/test/scala/chiselTests/BlackBoxImpl.scala
@@ -6,6 +6,7 @@ import java.io.File
 
 import chisel3._
 import chisel3.util.{HasBlackBoxInline, HasBlackBoxResource, HasBlackBoxPath}
+import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import firrtl.FirrtlExecutionSuccess
 import org.scalacheck.Test.Failed
 import org.scalatest.Succeeded
@@ -91,39 +92,29 @@ class UsesBlackBoxMinusViaPath extends Module {
 
 class BlackBoxImplSpec extends AnyFreeSpec with Matchers {
   val targetDir = "test_run_dir"
+  val stage = new ChiselStage
   "BlackBox can have verilator source implementation" - {
     "Implementations can be contained in-line" in {
-      Driver.execute(Array("-X", "verilog", "--target-dir", targetDir), () => new UsesBlackBoxAddViaInline) match {
-        case ChiselExecutionSuccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
-          val verilogOutput = new File(targetDir, "BlackBoxAdd.v")
-          verilogOutput.exists() should be (true)
-          verilogOutput.delete()
-          Succeeded
-        case _ =>
-          Failed
-      }
+      stage.execute(Array("-X", "verilog", "--target-dir", targetDir),
+                    Seq(ChiselGeneratorAnnotation(() => new UsesBlackBoxAddViaInline)))
+      val verilogOutput = new File(targetDir, "BlackBoxAdd.v")
+      verilogOutput.exists() should be (true)
+      verilogOutput.delete()
     }
     "Implementations can be contained in resource files" in {
-      Driver.execute(Array("-X", "low", "--target-dir", targetDir), () => new UsesBlackBoxMinusViaResource) match {
-        case ChiselExecutionSuccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
-          val verilogOutput = new File(targetDir, "BlackBoxTest.v")
-          verilogOutput.exists() should be (true)
-          verilogOutput.delete()
-          Succeeded
-        case _ =>
-          Failed
-      }
+      stage.execute(Array("-X", "low", "--target-dir", targetDir),
+                    Seq(ChiselGeneratorAnnotation(() => new UsesBlackBoxMinusViaResource)))
+      val verilogOutput = new File(targetDir, "BlackBoxTest.v")
+      verilogOutput.exists() should be (true)
+      verilogOutput.delete()
     }
     "Implementations can be contained in arbitrary files" in {
-      Driver.execute(Array("-X", "low", "--target-dir", targetDir), () => new UsesBlackBoxMinusViaPath) match {
-        case ChiselExecutionSuccess(_, _, Some(_: FirrtlExecutionSuccess)) =>
-          val verilogOutput = new File(targetDir, "BlackBoxTest.v")
-          verilogOutput.exists() should be (true)
-          verilogOutput.delete()
-          Succeeded
-        case _ =>
-          Failed
-      }
+      stage.execute(Array("-X", "low", "--target-dir", targetDir),
+                    Seq(ChiselGeneratorAnnotation(() => new UsesBlackBoxMinusViaPath)))
+      val verilogOutput = new File(targetDir, "BlackBoxTest.v")
+      verilogOutput.exists() should be (true)
+      verilogOutput.delete()
+      Succeeded
     }
   }
 }